Đề tài A low power high dynamic range broadband variable gain amplifier for an ultra wideband receiver

n out CCR s C g s CC R g s CCC CCg i i 

     + +

     + + + + + + ≅ 311 1 31 1 311 312 5.0 1 2 1 2 (4.5) With the Cadence simulation, the f -3dB of the multi-stage programmable current mirror vs. the current gain can be plotted as shown in Fig 4.8. The simulation setup is shown in Fig 4.7. The dimensions and the bias current values are the same as listed in 50 Table 3.3. Notice that for an M-stage programmable current mirror to obtain a total current gain of L, each current gain M LN = . Fig 4.7 Simulation setup for multi-stage programmable current mirror Fig 4.8 shows that with two or more programmable current mirror stages, to implement current gain of 5 A/A, their f -3dB all drop to less than 700MHz. Including the parasitic capacitance from the input stage which is also connected to the diode- connected node of the programmable current mirror, the overall f -3dB of the VGA may fall below the design requirement (>350MHz). Thus, to ensure enough bandwidth at a large gain variation, only one-stage programmable current mirror is chosen in this design. The details about the programmable current mirror are given in Chapter III. 51 Fig 4.8 f -3dB of the multi-stage programmable current mirror vs. current gain IV.3.4 Frequency-compensation scheme To ensure that even with all parasitic included the overall bandwidth of the VGA is still enough to meet the requirement, the frequency compensation is implemented. To explain the concept of this compensation and its effectiveness, we refer to the programmable current mirror in Fig 4.9. 52 Fig 4.9 Simplified schematic of the programmable current mirror From equation 3.15, and there are two poles in the programmable current mirror: ( ) ) nodeat (5.0 1 ,) node(at 2 31 2 1 1 1 DCCR C C g P m P + == ωω . 11333221111 and 2 where SBGSDBGDGDGSDBGDGS CCCCCCCCCCC +++=++++= We can cancel some parasitic capacitance at node C. The capacitive frequency compensation is shown in Fig 4.9. At node Vo, ignoring the output resistance of compensation transistor: ( ) ( ) C m m mCm Cm in o m XCoXminXmo C g s sg sCCg sCg V IG sVCIsVCVVgI + −≈ ++ −== ==+−+ and 0 (4.6) 53 Fig 4.10 Single-ended version of the compensation circuit and its small signal model So this is equivalent to a negative capacitor (-CC) and a negative resistor (-1/gm) connected in series to node C. This gives us a high-pass characteristic as shown in Fig 4.11. 54 (a) (b) Fig 4.11 Compensation effects on the current mirror As illustrated in Fig 4.11 (b), there exists a corner frequency gm /CC. If the corner frequency is higher than the frequency of the pole at node C, we should move this corner frequency to lower frequency to compensate the poles in our VGA. To reduce it, we can either increase CC or reduce gmc. In Figs 4.12 and 4.13, it is shown that increasing Cc and reducing gmc in a certain range, the bandwidth of the VGA is extended to higher frequency. But if we further reduce the corner frequency of the compensation to lower than the frequency of the pole at node C, the overall capacitance at that node becomes negative. It results in large peaking and extremely large group delay variation. So, the negative capacitance effects from our compensation scheme should not over-compensate the positive parasitic capacitance there. 55 Fig 4.12 Capacitance variation effects on frequency response Fig 4.13 gmc variation effects on frequency response 56 Fig 4.12 shows that by increasing compensation capacitor values from 120 to 240pF, the bandwidth of the VGA is extended. When the capacitor value reaches beyond 200pF, the group delay variation is larger than 200pS which is not tolerable by our design requirement. Therefore, the compensation capacitor should not be increased above certain level, and this level is restricted by the group delay variation requirement. Fig 4.13 indicates that by decreasing the transconductance of the transistor Mc, the bandwidth of the VGA can be extended. However, by further decreasing it to under a certain level, the group delay variation will be intolerable too as shown in Fig 4.12. Therefore, observe from Figs 4.12 and 4.13 that restricting by the group delay variation requirement (<200pS), the compensation will extend the f -3dB by approximately 50%. Because our VGA is in fully differential style, the capacitive frequency compensation is implemented in a differential version as well (see Fig 4.14 and Table 4.5). Fig 4.14 Implementation of the capacitive frequency compensation 57 Table 4.5 Dimension of the capacitive frequency compensation Ibias WMc CC 220µA 12µm 160fF IV.3.5 DC offset cancellation To fix the DC operating point at the output between M3 and M6, and to cancel out common-mode offset, an offset-cancellation circuit is used, as illustrated in Fig 4.3. M4 is half of the size of M3, (W/L)M4 = 1/2(W/L)M3, and M5 and M6 are identical. So the AC signals at A and B are cancelled, and only their common-mode DC values are left and are feedback to M6 and M3. Because of the size used here, the feedback DC current is exactly the amount needed to correct the operating point of M6 and M3 to its ideal level. Through this approach, disregarding how the DC bias current changes in the input stage, the output DC level is fixed. IV.3.6. Digital control circuit According to the discussion in the gain control scheme, there are 3 steps of coarse tuning and 8 steps of fine tuning. Hence, we can use 2-bit digital control for the coarse tuning and 3-bit digital control for the fine tuning, as illustrated in Fig 4.4. From Table 3.2, the digital gain control for the bias voltage of M2 in Fig 3.4 is identical to the thermometer code, the logic for which is given as: ( ) 21062152104 3321022112100 bbbsbbsbbbs bsbbbsbbsbbbs ++=+=+= =+=== (4.7) 58 Then, the digital control circuit is implemented, as in Fig 4.15. Fig 4.15 Digital control circuit IV.3.7 The dimension and bias current for the VGA The nominations of the components in the VGA are illustrated in Figs 4.2 and 4.3. The corresponding dimensions and bias currents for the VGA are shown in Tables 4.6 and 4.7. Please refer to Appendix B for the calculation details. Table 4.6 Dimensions and bias currents of the components of the VGA in the signal path WMp WMn Rs1 Rs2 Rload 78um 78um 3K ohm
Rsn1 4.5K ohm
Rsn1 300 ohm
Rsn2 450 ohm(Rsn2) 1.5K ohm Ibias Ib WM1 WM2 WM3 400µA 220µA 24µm 16µm 24µm L = 0.24um for all transistors 59 Table 4.7 Dimensions for the transistors in the bias control circuit (Fig 4.3) WMb1 WMb2 WMb3 WMb4 WMb5 WMb6 WMb7 2µm 4.8µm 4.8µm 4.8µm 4.8µm 1.68µm 0.72µm IV.4 Conclusion In this chapter, the design challenges and motivations of this VGA design are summarized. Complementary differential pairs with source degeneration are used as the input stage to achieve the good power-efficiency and maintain enough linearity. The programmable current mirror is proposed as the current amplification to further amplify the current, which has good programmability and frequency response. To cover the large variable gain range, gain tuning is further divided into coarse and fine tuning. Coarse tuning is obtained by changing the source degeneration resistor in the input stage; while fine tuning is achieved by varying the transistor dimension in the bias control circuit and hence changing the current amplification ratio. Both schemes are programmed by the digital gain control. Capacitive frequency compensation is adapted to further extend the bandwidth of the VGA, and a DC offset cancellation is used to fix the DC output voltage level and cancel out the offset voltage due to gain changing or mismatch effects. Overall, the proposed VGA structure is able to achieve large variable gain rang, very large bandwidth with very low power consumption, and very small group delay variation. The simulation result of this design will be given in the next chapter to justify the performance of this VGA. 60 CHAPTER V SUMMARY OF RESULTS The VGA has been designed in the IBM 6HP 0.25µm CMOS process. Simulation results are included in this chapter. The experimental results for the prototype fabricated in the same process are presented. V.1 Design summary The design specifications for the VGA are summarized in Table 5.1. Table 5.1 Design specifications for VGA Technology IBM6HP 0.25µm CMOS process Variable gain range 0 ~ 42dB, 2dB/step Bandwidth (f -1dB) > 264MHz Linearity (IIP3) > -15dBm Noise (Noise Figure) < 25dB Group delay variation < 200pS Power consumption < 20mW V.2. Simulation setup Two simulation setups are performed, these are: 61 1) Use a buffer to provide the voltage level shift for the ADC’s 0.3V input DC voltage level. In this case, the load resistors are still chosen as the previous design value which is 2K
. 2) Without using a buffer to ADC while the VGA output is directly connected to the output pads which have large capacitance (about 5pF). The load resistors are external resistors outside the chip, and to ensure VGA’s bandwidth will not get degraded by the pole from the resistance from the load and the large parasitic capacitance of the pads, the load resistors are intentionally made accordingly smaller—100 ohm for this case . (a) With buffer to ADC stage (Rload = 2K ohm) (b) Without buffer to ADC stage (Rload = 100 ohm) Fig 5.1 Simulation setup 62 Comparing these two setups, we realize that the maximum DC gain from the second setup will be 16dB instead of 42dB because its load resistor is 20 times smaller than that of the first case. However, it can be still verified the functionality of the VGA based on the second setup, as the VGA current amplification range in both setups is the equal, just the load resistor plays a multification factor to determine the final absolute value of the gain. These two setups are shown in Fig 5.1. The dimensions of the VGAs used in the different setups are listed in Table 5.2 as shown. Table 5.2 Dimensions of the VGAs for different setups With buffer to ADC stage Mp Mn Rs1 Rs2 Rload M1 M2 M3 78/0.24 (µm) 78/0.24 (µm) 3K ohm 4.5K ohm 300 ohm 450 ohm 2K ohm 24/0.24 (µm) 16/0.24 (µm) 24/0.24 (µm) Ibiasn* Ibiasp* 910µA 1040µA Mb1 Mb2 Mb3 Mb4 Mb5 Mb6 Mb7 2/0.24 (µm) 4.8/0.24 (µm) 4.8/0.24 (µm) 4.8/0.24 (µm) 4.8/0.24 (µm) 1.68/0.24 (µm) 0.72/0.24 (µm) Without buffer while directly connected to the output pads Mp Mn Rs1 Rs2 Rload M1 M2 M3 78/0.24 (µm) 78/0.24 (µm) 3K
4.5K
300
450
100
As the same as the case with buffer to ADC Ibiasn* Ibiasp* Mb1 Mb2 Mb3 Mb4 Mb5 Mb6 Mb7 1170 µA 1040µA As the same as the case with buffer to ADC 63 In the following sections, the post-layout simulation results of these two setups will be shown and discussed. V.3 Simulation results V.3.1 Explanation of simulation terminologies The simulation results provided are collected from the post-layout simulations, in which all the parasitic capacitors are extracted except for the well-to-subtract parasitic capacitance. Measurement setting and simulated terms are defined as follows. (1) -1dB bandwidth (f -1dB) This is the bandwidth in which the voltage gain is 1dB below the DC gain. It indicates the gain flatness of the VGA within the useful bandwidth. (2) -3dB bandwidth (f -3dB) This is the bandwidth in which the voltage gain is 3dB below the DC gain, and it is commonly used as a critical specification in many VGA designs. (3) Linearity and distortion Consider a nonlinear system described by )()()()( 332210 txatxatxaaty +++= (5.1) where y (t) and x (t) are the output and input of the system respectively. Consider ( ) ( )tAtAtx 21 coscos)( ωω += , where 1 and 2 are two frequencies very closed to each others around the frequency of interest, substitute this into equation 5.1 yields 64 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( )[ ] ( ) ( )[ ] ( )[ ] ( )[ ] ( )[ ] ( )[ ] ( ) ( )tAatAa t Aa t Aa t Aa t Aa tAa tAatAatAa t AaAatAaAaAaaty 2 3 3 1 3 3 12 3 3 21 3 3 12 3 3 21 3 3 21 2 2 21 2 22 2 2 1 2 2 2 2 3 11 2 3 1 2 20 3cos 4 33cos 4 3 2cos 4 32cos 4 3 2cos 4 32cos 4 3 cos cos2cos 2 2cos 2 cos 4 9 cos 4 9 ωω ωωωω ωωωωωω ωωωω ωω

     +

     ++

     ++

     +−

     +−

     +− +++

     +

     +

     ++

     +++= (5.2) The third-order intercept point (IIP3): It is defined as the input signal power level at which the fundamental component intercepts with the third-order intermodulation component. From equation 5.2, ( ) 3 1 3 3 33 31 3 4 4 3 a a AAaAa IIPIIPIIP =

     = (5.3) Also, the third-order intermodulation distortion IM3 is defined as 2 1 3 4 3 3 A a a IM = (5.4) Comparing equation 5.3 and 5.4, we can relate IIP3 with IM3 as follows, ( ) ( ) 2 )()()( log20log20log20/ 4 3 / 3 3 3 22 33 22 1 322 3 dBIMdBmAdBmA IMAAIMAA a a AA IIP IIPIIP −= −==

      = (5.5) where A is the input signal magnitude in dBm unit. By measuring IM3 at a certain input signal level, IIP3 can be obtained accordingly. 65 (4) Input referred integrated noise Input referred noise is the noise collected from the VGA output divided by the gain of the VGA. In this simulation, the input referred integrated noise is integrated from DC to 250MHz. (5) Signal-to-Noise-Ratio (SNR) Low noise is an important concern if the input signal is very small and the bandwidth of interest is very wide. Since we are interested in a very high frequency, the contribution from the 1/f noise at a lower frequency can be neglected. Signal-to-Noise- Ratio is 2 , 2 ,log10 inn rmsin V V SNR = (5.6) where rmsinV , is the root-mean-square value of the input signal, and innV , is the equivalent input referred noise voltage. (6) Noise Figure (NF) The most commonly accepted definition of Noise Figure is given in equation 5.7. Noise out in SNR SNR Figure = (5.7) Noise Figure is a measure of how much the SNR degrades as the signal passes through a system. And it can be written as:

     ⋅ +⋅= BWkTR INNF s4 1log10 2 (5.8) 66 where IN is short for integrated input referred noise voltage. For Rs = 50
 and BW = 250MHz, 2101096.14 VBWkTRs −×=⋅ (7) Group Delay The Group Delay is defined as the rate of change of the total phase shift with respect to the angular frequency: Group Delay = ω θ ∂ ∂ (5.9) It also is the time delay through the system for a sine wave pulse. If the group delay is non-uniform and varies with the sine-wave frequency, the time-domain response to a sharp input-signal change may show overshoot or ringing. Thus, a perfectly uniform group delay is equivalent to a perfectly linear phase response. (8) Figure of Merit (FOM) A Figure of Merit (FOM) is defined such that this VGA’s performance can be compared with other VGA designs fairly. Based on the design requirements, the FOM should include the maximum DC voltage gain ( )0( ,MAXVA ), the -3dB frequency bandwidth ( dBf 3− ), the technology, the power consumption, and the silicon area of the VGA. With concerns of linearity and noise, the Signal to Noise Ratio should be included in the FOM as well, which indicates the ratio between the input signal level (under sufficient linearity level) and the input referred noise voltage. Thus, the FOM can be defined as 67 AreaPower TechnologySNR)0( 3, × ××× = − dBMAXV fAFOM (5.10) Next, the post-layout simulation results are presented in detail. V.3.2 Layout The VGA is laid out for I/Q channels, and includes analog and digital parts as shown in Fig 5.2. Each VGA occupies silicon area of 22 mm0154.0m15400m110m140 ==× , and the total area of I/Q channels is approximately 0.03mm2. Fig 5.2 Layout view of the I/Q channels of the VGA 68 V.3.3 AC response The VGA post-layout simulation results of the AC response are shown in Figs 5.3 through 5.8d. It achieves 0 to 42dB with 2dB/step for this VGA with both simulation setups (one with a buffer to ADC and the other without). For the setup with a buffer to ADC, it achieves f -1dB > 321MHz (f-3dB= 474MHz), and the group delay for all cases is less than 150 pS. As for the setup without a buffer with the VGA output directly tied to the pads, it achieves f -1dB > 290MHz (f-3dB= 411MHz), and the group delay for all cases is less than 110 pS for all gain cases. Therefore, all results meet the requirements, as summarized in Tables 5.3 and 5.4. Table 5.3 Post-layout AC response simulation results vs. system requirements With buffer to ADC Gain Range (dB) Bandwidth (MHz) Group Delay(pS) Post-Layout Simulations 321[f -1dB] (474[f- 3dB]) 146 System Requirements 0 ~ 42dB 2dB/Step >264 [f -1dB] <200 Without buffer to ADC Gain Range (dB) Bandwidth (MHz) Group Delay(pS) Post-Layout Simulations 311[f -1dB] (290[f- 3dB]) 108 System Requirements 0 ~ 42dB 2dB/Step >264 [f -1dB] <200 69 Table 5.4 AC response a. With Buffer to ADC (Rload = 2K ohm) 2dB/Step, 0 ~ 42dB Ideal Gain (dB) Real Gain (dB) f -3dB (MHz) Group Delay(pS) 42 42.65 474 (321[f -3dB]) 45 36 35.9 492 86 30 30.14 512 110 24 24.3 528 102 18 18.14 540 131 12 11.92 548 136 6 6.1 562 139 0 0.368 580 146 b. Without buffer to ADC (Rload = 100 ohm) Ideal Gain (dB) Real Gain (dB) f -3dB (MHz) Group Delay(pS) 16 16.65 411(290 [f -3dB]) 39 10 10.8 432 44 4 4.3 459 67 -2 -1.4 489 93 -8 -7.3 490 89 -14 -13.9 496 96 -20 -20.4 512 102 -26 -26.3 520 108 70 (1) Frequency response based on VGA setup with buffer to ADC Fig 5.3 Gain steps from 30dB to 42dB Fig 5.4 Gain steps from 16dB to 28dB 71 Fig 5.5 Gain steps from 0dB to 14dB (2) Frequency response based on VGA setup without buffer to ADC Fig 5.6 Gain steps from 2dB to 16dB 72 Fig 5.7 Gain steps from -12dB to 0dB Fig 5.8 Gain steps from -26dB to -14dB 73 V.3.4 Noise (1) SNR The Signal-to-Noise-Ratio (SNR) is defined previously in equation 5.6 as the ratio between the root-mean-square values of the input signal to the corresponding equivalent input-referred noise voltage. 2 , 2 ,log10 inn rmsin V V SNR = (5.6) where rmsinV , is the root-mean-square value of the input signal, and innV , is the equivalent input referred noise voltage. VGA with maximum gain setting has the smallest input signal. Therefore, noise at a 42dB gain setting is characterized at this section. As the differential output-signal level of the VGA is fixed to 1Vpp, and the equivalent input referred noise power ( 2,innV ) is 3.6×10-9V2/Hz at 42dB gain, so the SNR is given as 9 2 20 42 2 , 2 , 106.3 1022 1 log10log10 − ⋅


      ⋅ == inn rmsin V V SNR = 33.4dB (2) Noise Figure The Noise Figure (NF) can be written as:

     ⋅ +⋅= BWkTR INNF s4 1log10 2 (5.8) 74 where IN is short for Integrated Input Referred Noise Voltage. For RS=50 ohm and BW = 250MHz, 2101096.14 VBWkTRS −×=⋅ . Thus, we calculate the Noise Figure based on IN as shown in Fig 5.9. As expected, the Noise Figure degraded from high-gain to low-gain cases as shown in Fig 5.9. The worst Noise Figure for the VGA with a buffer to ADC is 18.7dB; while for the case without a buffer, it gives 20.1dB for the worst case. So, both cases meet the system specification which requires the Noise Figure to be less than 25dB for all gain steps. Noise Figure for different gain 18.7 18.2 17 15.6 14.5 13.8 12.9 12.6 10 11 12 13 14 15 16 17 18 19 20 0 6 12 18 24 30 36 42 48 Gain levels (dB) No is e Fi gu re (dB ) (a) With buffer to ADC (Rload = 2K
) Fig 5.9 Noise Figure for different gain levels 75 Noise Figure for different gain 20.1 19 17.8 16.5 15.3 14.5 14 13.6 10 11 12 13 14 15 16 17 18 19 20 21 -26 -20 -14 -8 -2 4 10 16 22 Gain levels (dB) No is e Fi gu re (dB ) (b) Without buffer to ADC (Rload = 100
) Fig 5.9 Continued V.3.5 Linearity Because the output signal level is fixed by the VGA, increasing the gain in the VGA corresponds to lower input signal level, which relaxes the linearity requirement of the VGA. In other words, the most critical case to ensure good linearity in the VGA should be the lowest gain case, which corresponds to the largest input signal level. Therefore, the VGA should be designed to posses improving linearity when gain is reduced; that is the reason more source degeneration resistance in the lower gain case are 76 turned on. IIP3 for different gain settings is plotted in Fig 5.10. As expected, the better linearity is achieved in lower gain cases. The worst case for IIP3 is at 42dB, which is -6.3dBm, and is better than the required -15dBm. IIP3 for Different Gain Levels 21.1 18.6 11.3 4.25 -0.95 -4.85 -5.4 -6.3 -10 -5 0 5 10 15 20 25 0 6 12 18 24 30 36 42 48 Gain Levels (dB) IIP 3 (dB m ) (a) With buffer to ADC (Rload = 2K ohm)
     fffiffiflffi !"ff     
 #      fifl                    fl                     fl   $&%('*),+ $&%-%.)-'*/ $0%(12)232/ $4' $5% /2)-6 6*)-7*/ %-% 809;: 809(< 84: < : 9(< 9;: 84=->?8*=-@A8*=2 82@ 9E= 9(C GIHJ KML&NPO0NQ RSTVUXW G H J K L0N O&N Q RYS T UfiWG H J K L N O N Q R S T U W G H J K L N O N Q R S T U W Z Z[ \ ] ^ _ ` a Z Z[ \ ] ^ _ ` a Z Z[ \ ] ^ _ ` a Z Z[ \ ] ^ _ ` a (b) Without buffer to ADC (Rload = 100 ohm) Fig 5.10 IIP3 for different gain levels 77 V.3.6 Power consumption The maximum power consumption happens at the highest gain case—42dB, which only consumes 9.5mW and is way below the 20mW required by the system as shown in Fig 5.11, because the power efficient complementary differential pairs are used as the input stage. Fig 5.11 Power consumption V.4 Experimental results Fig 5.12 VGA testing pins arrangement 78 Fig 5.13 VGA input/output testing setup The testing setup is shown in Figs 5.12 and 5.13. The VGA is fabricated in IBM 6HP 0.25m CMOS technology. To convert single-ended input signal from the signal generator to the differential inputs for the VGA, balun (an abbreviation for balanced to unbalanced) is used. The ratio of the number of balun turns from single end to the differential ports is 1:4. Because broadband matching is required, only resistive instead of impedance-matching networks are used to match the output impedance of the signal generator. To convert the differential output signal from the VGA into the single-ended signal required by the measurement of the spectrum analyzer, a 4:1 balun is used at the output of the VGA. The 47pF capacitors are used for the AC coupling so that the input common-monde voltage is set by the input common-mode voltage level which is 1.25V for this design, and the output common-mode voltage is fixed at the middle of the power supply voltage to maximize the output voltage swing. For the measurement, a spectrum 79 analyzer with 50 ohm input impedance is used to measure the frequency response. The supply voltage is 0 to 2.5V. The testing shows a gain variation from -18dB to 14dB, with a 2dB/step. Including the gain loss of approximately 2dB from the balun (transformer), the maximum gain is as we expected as the post-layout simulation of 16dB for maximum gain with a 100 ohm load resistor (with 2K ohm, it will be 42dB). The -1dB frequency is from 266 to 293MHz, all above 264MHz, but a little bit short than the post-layout simulation (288~ 315MHz). The IIP3 are closed to the post-layout simulation results too. V.4.1 Experimental results for the AC response of the VGA The results are listed and illustrated in Table 5.5 and the remaining figures in the chapter. As mentioned previously, to avoid the bandwidth reduction caused by the pole from the large parasitic capacitance of the pad and the load resistor, a 100 ohm resistor is used as the load instead of 2K ohm. With this test setting, the experimental results show a gain range from -18dB to 14dB with the 100 ohm load resistor. Including the gain loss from the balun which is about 2dB, the above gain range corresponds to a gain range of 10 to 42dB with 2K ohm load resistor. We can also compare the DC gain of the testing results with the ideal DC gain steps desired to get an idea of the accuracy of the gain steps. In Table 5.5, it shows that, regarding the gain step accuracy, the worst case has a 0.73dB deviation from the ideal case (at -2dB ideal case, the experimental result shows - 1.2783dB). Thus, we can conclude that the deviations of gain-step from our desired values are all within the 1dB range. This further justifies that the programmable current 80 mirror proposed in this design can be accurately controlled to provide the desired gain variation at least to 2dB/step. As for the bandwidth, the -1 dB bandwidth (f -1dB) is defined previously to ensure the gain flatness within the useful bandwidth. Hence, we desired to have f -1dB at least larger than 264MHz for all cases to cover the entire band of interest. Among all the gain steps, the smallest f -1dB is about 266MHz and the largest is about 293MHz. These results verify that this design has enough bandwidth to cover the desired band and that the bandwidth is relatively constant along the whole gain range. The large and constant bandwidth is benefit from the good frequency response of the programmable current mirror and the capacitive frequency compensation, as demonstrated in Chapter IV. Besides, comparing to the post-layout simulation results, it can be also observed that the deviations of the gain steps between the post-layout simulation and the experimental results are all within the 2dB range, which indicates that the IBM 6HP design-kit includes relatively accurate models of parasitic effects of the components and thus provides designers a close estimation between the simulation results and the real performance of the design on the silicon. 81 Table 5.5 Testing results for VGA AC response Post-layout simulation Testing Gain steps (dB) DC Gain (dB) f -1dB (MHz) DC Gain (dB) f-1dB (MHz) -18 -18.3 315 -18.687 291.15 -16 -15.92 310 -16.095 284.06 -14 -13.9 304 -14.273 282.4 -12 -12.1 320 -12.2 291.9 -10 -9.9 316 -10.068 291.105 -8 -7.3 305 -7.27 281 -6 -5.92 310 -5.6832 281.875 -4 -4.05 307 -4.168 288.56 -2 -1.4 298 -1.2783 276.68 0 0.24 303 -0.595 288.2 2 2.1 307 2.3413 293.57 4 4.3 305 4.2174 283.67 6 5.95 302 6.011 270 8 8.02 302 7.9052 267.87 10 10.8 294 9.108 270.48 12 11.78 299 11.492 270.22 14 13.85 288 13.561 266.7 The measurement results of the frequency response of the gain settings of 14, 12, 10, 8, and 6dB with a 100 ohm load resistor is shown in Fig 5.14. Including the loss from the balun, which is about 2dB, this group of gain settings correspond to 42, 40, 38, 36, and 34dB with the 2K ohm load resistor. Because we are considering the whole 82 VGA gain range, this group of gains is high gain stages, the -1dB frequency of this group of gain settings is between 266 to 270MHz as illustrated in Table 5.5 previously and are relatively low compared to other low gain cases. Table 5.5 also shows that the gain accuracy of this group of gains is below 0.9dB derivation from the ideal DC gain values. This gain derivation is still tolerable because it is less than the minimum gain step (2dB/step) of the VGA. Fig 5.14 Frequency response of gain settings of 14, 12, 10, 8, and 6dB The measurement results of the frequency response of the gain settings of 4, 2, 0, -2, -4, and -6dB with a 100 ohm load resistor are shown in Fig 5.15, and correspond to 32, 30, 28, 26, 24, and 22dB with the 2K ohm load resistor. The -1dB frequency of this 83 group of gain settings are between 298 to 310MHz. The gain accuracy of this group of gains is all below 0.73dB derivation from the ideal DC gain values, and this is tolerable because it is still fall below the minimum gain step (2dB/step) of the VGA. Fig 5.15 Gain setting of 4, 2, 0, -2, -4, and -6dB The measurement results from the frequency response with the gain settings of - 8, -10, -12, -14, -16, and -18dB with a 100 ohm load resistor are shown in Fig 5.16, and they correspond to 20, 18, 16, 14, 12, and 10dB with the 2K ohm load resistor. Their f - 1dB frequency of this group of gain settings is between 305 to 315MHz, which is higher than the rest gain settings because this is a low gain-stage group. Table 5.5 also shows that the gain accuracy is below the 0.7dB derivation from the ideal DC gain values, which is higher than the rest of the gain settings because this is a low gain-stage group. 84 Fig 5.16 Gain setting of -8, -10, -12, -14, -16, and -18dB We couldn’t accurately measure the rest of the gain settings between -26 to - 20dB with a load resistor 100 ohm, which correspond to 0 to 8dB with load resistor of 2K ohm. One reason is that the chip included this VGA design has a malfunction in its ESD protection pins, its ESD_VDD and ESD_GND are shorted together. This mistake severely limits the control voltage range of the digital control circuit to be less than two times the diode’s forward bias voltage (about 1.4V). In a result, some of gain stages may miss if the digital circuit can not be fully turned on or off. The measured frequency response of the maximum and minimum gain steps are shown in Figs 5.17 and 5.18 respectively. 85 Fig 5.17 Gain setting of -18dB: Av(0) = -18.687dB, f -1dB = 291.15MHz Fig 5.18 Gain setting of 14dB: Av(0) = 13.561dB, f -1dB = 266.7MHz 86 V.4.2 Experimental results of the IIP3 To measure the IIP3, the two-tone test is performed with one tone at 240MHz and the other at 260MHz. By sweeping the input signal’s power level, two sets of data are recorded. One set of data is for the output power level of the fundamental tone (at 240 and 260MHz), and the other set of data is for the output power level of the third harmonic (at 220 and 280MHz) due to the intermodulation of the input two tones. By recording several of those data at different input power level, the curve of the power levels of the fundamental tones and the third harmonic tones changing along the varied input signals can be obtained. Hence, using a straight line to interpolate these two curves, the intersection point of the two curves can be found. The corresponding input signal power level is the IIP3. The whole procedure is illustrated in Fig 5.19. Fig 5.19 Measure IIP3 with interpolation 87 According to this measurement procedure, the IIP3 of different gain stages are obtained as shown in Fig.5.19. The measured IIP3 of the maximum and minimum gain steps are summarized in Table 5.6. Notice that, the balun (transformer) loss is about 2dB, and the loss from the wire and connectors of the spectrum analyzer is about 6dB, so the total loss is 8dB. We need to deduct this amount from IIP3 calculation. The post- layout simulation results are shown in Fig 5.20 to compare with the experimental results. Table 5.6 IIP3 testing results Pin(dBm) -10 -8 -6 -4 -2 0 IIP3(dBm) Gain(dB) 1st -36 -33.7 -31.8 -30 -28.3 -26.7 8 -18 3rd -72 -66 -60.1 -54.8 -49.2 -44.8 Pin(dBm) -24 -22 -18 -16 -14 -12 IIP3(dBm) Gain(dB) 1st -18.7 -16.89 -14.9 -13 -11.2 -9.5 -12.5 14 3rd -41.77 -35.85 -29.9 -24.1 -19.4 -14.9 Experimental results: IIP3 8 4.5 3 -2 -4.5 -5 -11.5 -12 -13.5 -15 -10 -5 0 5 10 -22 -18 -14 -10 -6 -2 2 6 10 14 18 Gain levels (dB) IIP 3 (dB m ) Fig 5.20 Testing results of IIP3 vs. gain levels 88 Post-layout simulation results: IIP3 9.25 5.9 -1 -3 -10.85 -11.5 -13.6 -15 -10 -5 0 5 10 15 -26 -20 -14 -8 -2 4 10 16 22 Gain levels (dB) IIP 3 (dB m ) Fig 5.21 Post-layout results of IIP3 vs. gain levels For the VGA gain range from -18 to 14dB, the IIP3 is from 8 to -13.5dBm, as illustrated in Fig 5.21. Comparing Figs 5.20 and 5.21, the experimental results show that there are about 1 ~ 2dBm loss in IIP3 from its post-layout simulation results. Overall, for all gain steps, their IIP3s are all above -14dBm, which is enough for the system requirement of IIP3 > -15dBm for all gain steps. V.4.3 Noise characterization Low noise is an important concern if the input signal is very small and the bandwidth of interest is very wide. Since we are interested in a very high frequency (up to 250MHz), the contribution from the 1/f noise at a lower frequency can be neglected. In this measurement, the spectrum analyzer collects the noise power within the Resolution Bandwidth (RBW). The noise power per Hz at the output, 2nov , is obtained by 89 dividing the noise power on the spectrum analyzer, 2 ,spectrumnv , by the RBW; hence the noise power per Hz is RBW v v spectrumn no 2 ,2 = (5.11) In a further step, the Noise Figure can be calculated in equation 5.8 as demonstrated in previously,

     ⋅ +⋅= BWkTR INNF s4 1log10 2 (5.8) where IN is short for Integrated Input Referred Noise Voltage Given that in the measurement, RBW = 1MHz, and with equation 5.11, it yields 2 2 , 2 2 2 )0( 250 1 )0( v spectrumn v no A MHz MHz v A BWvIN ×

      = × = (5.12) Also, it can be also found that, with Rs = 50
, BW = 250MHz, 4kTRs×BW = 1.96 ×10-10 V2. Substitute this result into equation 5.12 yields ( )

      ×× × +⋅= −102 2 , 1096.10 2501log10 v spectrumn A vNF (5.13) With equation 5.12, the Noise Figure for each gain stage based on the noise power output measurement result from the spectrum analyzer can be obtained. The measured output noise power from the spectrum analyzer of the maximum and minimum gain steps are shown in Figs 5.22 and 5.23. 90 Fig 5.22 Av(0) = 14dB, equivalent output noise level = -79.6dBm, NF = 14.8dB Fig 5.23 Av(0) = -18dB, equivalent output noise level = -106dBm, NF = 20.53dB With the output noise power for different gain stages measured, using equation 5.13, the Noise Figure for different gain settings can be calculated. A comparison of 91 Noise Figure results from the measurement with those from the post-layout simulation is shown in Fig 5.24. NF with different gain settings 14.8 15.315.6 16.1 17.1 18.0 19.1 19.7 20.5 13.814 14.3 14.6 15.3 16.5 17 17.8 18.8 12.0 14.0 16.0 18.0 20.0 22.0 -22 -18 -14 -10 -6 -2 2 6 10 14 18 Gain levels (dB) NF (d B ) Experimental Post-layout Fig 5.24 Noise Figure (NF): experimental result vs. post-layout simulation results As seen in Fig 5.24, the Noise Figure varies from 14.8dB to 20.5dB for all gain settings, and they all fall in the required range of the system design specifications, which is less than 25dB for all gain cases. Because the noise performance is a more important concern in the very small input signal cases as mentioned before, the noise figure at the maximum gain setting—14dB—should be guaranteed to be lower than the requirement. The testing results show that the noise figure at the maximum gain is much below the requirement of NF < 25dB. For the lower gain cases, even though the noise figure is degraded, and the VGA introduces more noise into the signal it processing, the input 92 signal levels are relatively higher and are more immune to the noise than the very small signal level at the high gain cases. So, from the system design point of view, as long as they are all below the required noise level, the degradation of noise performance in the lower gain cases is still tolerable,. Comparing the experimental results with post-layout simulation results, the experimental results deviate from the simulation by about 1 ~ 2dB, which again indicates the IBM 6HP design-kit has a relatively accurate model on the noise performance of the circuit. V.5 Summary of results and comparison As mentioned, comparing the Figure of Merit (FOM) of all the references with this work is a more fair approach to compare the overall performance of these VGAs because it includes the maximum gain range, -3dB bandwidth, signal-to-noise-ratio (SNR) and the power consumption performance altogether. AreaPower TechnologySNR)0( 3, × ××× = − dBMAXV fAFOM (5.10) Notice that the commonly used units for each specification are different from the International Standard Unit, for example, AV,MAX(0)’s unit is dB. So, when calculating the FOM, all the specifications are converted into the International Standard Unit. Finally, as the FOM will be a very large number if it is still in the International Standard Unit, it can be expressed in dB instead. Table 5.7 and Figure 5.25 illustrate the results. 93 Table 5.7 Figure of Merit (FOM) comparison AV,MAX(0) (dB) f-3dB (MHz) SNR (dB) Power (mW) Technology Area (mm2) FOM (dB) [4] 40 495 12.65 54 0.35µm CMOS 0.15 259 [8] 11 380 35 64 0.25 µm CMOS 2 223 [9] 34 2000 35 40 0.18 µm CMOS 0.7 271 This work 42 425 30 9.5 0.25 µm CMOS 0.015 310 Figure of Merit (FOM) 0 50 100 150 200 250 300 350 [2] [8] [9] This work FO M (dB ) FOM (dB) Fig 5.25 Figure of Merit (FOM) comparison 94 Fig 5.25 shows that this work has the highest Figure of Merit, mainly due to the highest maximum gain, largest bandwidth, and lowest power consumption among the VGAs in that comparison. In summary, from the experimental results and comparing with the state-of-the- art VGA designs in the literature, the proposed VGA posses: (1) Comparable gain variable range and the smallest gain steps; (2) Comparable bandwidth with other designs; (3) Occupies the smallest area; (4) Has the best power consumption among all designs; (5) Comparable or better than other designs in linearity and noise performance. 95 CHAPTER VI CONCLUSION A fully differential CMOS Variable Gain Amplifier (VGA) consisting of complementary differential pairs with source degeneration, current gain stage with programmable current mirror, and resistor loads is designed for high frequency and low power communication applications, such as UWB receiver system. The gain can be programmed from 0 to 42dB of 2dB/step with -3dB bandwidth greater than 425MHz for all range of gain. The Third-Order Input Intercept Point (IIP3) is above -7dBm for 1Vpp differential input and output voltages. These low distortion broadband features are benefited from the large linear range of the differential pair with source degeneration and the low impedance internal nodes in the current gain stages. In addition, common-mode feedback is not required because of these low impedance nodes. Due to the power efficient complementary differential pairs as input stage, the power consumption is minimized (9.5mW) for all gain steps. The gain-control scheme includes of fine tuning (2dB/step) by changing the bias voltage of the proposed programmable current mirror, and coarse tuning (14dB/step) by switching on/off the source degeneration resistors in the differential pairs. Capacitive frequency compensation scheme is used to further extend the VGA bandwidth. 96 The VGA has been designed in the IBM 6HP 0.25µm CMOS processes. Experimental results demonstrated closed results as the post-layout simulation as expected. This VGA topology, benefiting from its features such as ultra-low power consumption, small die area, large gain range and bandwidth, low distortions, can be broadly adopted into other immerging communication systems as well. 97 REFERENCES [1] R. Gomez and A. A. Abidi, “A 50 MHz CMOS Variable Gain Amplifier for magnetic Data Storage Systems,” IEEE Journal of Solid-State Circuits, vol.35, no.6, pp.935-939, Jun. 1992. [2] R. Gomez and A. A. Abidi, “A 50 MHz Variable Gain Amplifier Cell in 2µm CMOS,” in Proc. IEEE Custom IC Conference, May 1991, pp.9.4.1-9.4.4. [3] T.-W. Pan and A. A. Abidi, “A 50dB Variable Gain Amplifier Using Parasitic Bipolar Transistors in CMOS,” IEEE Journal of Solid-State Circuits, vol.24, no.4, pp.951-961, Aug. 1989. [4] S.T Tan, and J. Silva-Martinez, “A 270 MHz, 1Vpk-pk, Low-Distortion Variable Gain Amplifier in 0.35µm CMOS Process,” Analog Integrated Circuits and Signal Processing, vol.38, no.2, pp.307-310, Feb.2004. [5] Y. Zheng, J. Yan, and Y. Xu, “A CMOS dB-Linear VGA with Pre-Distortion Compensation for Wireless Communication Applications,” in Proc. International Symposium on Circuits and Systems, May 2004, vol.1, pp.813-816. [6] A. Thanachayanont and P. Naktongkul, “Low-Voltage Wideband Compact CMOS Variable Gain Amplifier,” Electronics Letters, vol. 41, no. 2, pp.51-52, Jan. 2005. [7] J. Silva-Martinez, J. Adut, J. M. Rocha-Perez, M. Robinson and S. Rokhsaz, “A 60mW 200 MHz Continuous-Time Seventh-Order Linear Phase Filter with On-Chip 98 Automatic Tuning System,” IEEE Journal of Solid-State Circuits, vol. 38, no.2, pp.216-225, Feb. 2003. [8] O. Watanabe, S. Otaka, M.Ashida, and T. Itakura, “A 380MHz CMOS Linear-in-dB Signal-Summing Variable Gain Amplifier with Gain Compensation Techniques for CDMA Systems,” in VLSI Circuits Digest of Technical Papers, Jun. 2002, pp.136- 139. [9] C.-H. Wu, C.-S. Liu and S.-L. Liu, “A 2 GHz CMOS Variable Gain Amplifier with 50dB Linear-in-Magnitude Controlled Gain Range for 10GBase-LX4 Ethernet,” in IEEE International Solid-State Circuits Conference, vol. 1, Feb. 2004, pp.584-541. 99 APPENDIX A DETERMINE THE DIMENSIONS FOR THE PROGRAMMABLE CURRENT MIRROR In this appendix, it will be shown how equation (3.12) is obtained. Let us make some assumptions and observations (as shown in Fig 3.4.) (1) Assume, M1 and M2 have identical dimensions while that of M3 is )/(MLW (2) Make an equivalent transistor for all the transistors turned on in the bias control circuit, call it Mb with dimension )/(NLW . (3) Assume that the bias current for the bias control circuit is correlated to that of the programmable current mirror. Set Ibias for the current mirror, then Iref = K× Ibias in the bias control circuit, where K is a constant current gain factor. Fig A.1 Bias Transistors to generate seven gain steps for programmable current mirror 100 First, notice that 231231 then DSATDSDSATGSDSGS VVVVVV =+=+ , where VDSAT = VGS – Vth. Since M1 and Mb operate in the saturation region while M3 operates in the triode region, their drain-source currents are given by [ ] [ ])(1 2 1 2 )(1 2 1 2 2 3 333 11 2 11 DSATbDSbDSATbOXnref DS DSDSATOXnD DSATDSDSATOXnD VVV NL WCI VVV ML WCI VVV L WCI −+=

      −= −+= λµ µ λµ (A.1) From Fig 3.9, 1111 ththGSDSDSATDS VVVVVV =+−=−
( ) [ ] 12 1 2 321 thDSDSATOXnD VVVL WCI λµ +−=∴ (A.2) [ ] 1 2 1 2 33 thDSATOXnrefDSATbDSAT VVNL WCIVV λµ +=∴=
(A.3) 31 ** DDref IKIKI == (A.4) Combining equation A3.1, A3.3, and A3.4, we obtain ))/(1( 0 2 2 1 2 33 2 333 2 3 2 3 2 3 33 N KMNVV V NK MVVVV N V VV M K DSATDS DSATDSDSATDSDSAT DS DSDSAT − −= =+−=

      − (A.5) Combining equation A3.2, A3.3, and A3.4, we obtain ( ) 33223232 11 DSATDSDSATDSATDSDSAT VNKVVVNVVK =−=− (A.6) Substituting equation A3.5 into A3.6, we have ))/(11(32 N KMN KN VV DSATDSAT − −+= (A.7) 101 The low frequency current gain of programmable current mirror is given by ( )232 2 2 DSDSAT DSAT in out VV V i i − = (A.8) Substituting equation A3.6 and A3.7 into A3.8, yields ( )21 MNKNK i i in out −−+= (3.12) Where ( ) ( ) ( ) ( ) bias ref b I I K LW LWN LW LW M === , / / , / / 1 3 1 Therefore, the low frequency current gain of the programmable current mirror is a function of the aspect ratios of M1, M3 and Mb, and the ratio between Iref and Ibias. In the approach used in this design, ( ) ( ) biasref IILWLW /,/,/ 31 are all fixed. By varying ( )bLW / , different current gains can be obtained. 102 APPENDIX B THE DIMENSIONS AND CURRENT BIAS FOR THE VGA 1) Calculation of the load resistance As -3dB frequency (f -3dB)>350MHz, to leave some margin, choose f-3dB = 400MHz. From this, we can estimate the output resistance we need. ( )outoutdB CRf /13 =− . As we use current mirror connecting to the output resistor, their parasitic capacitor determines Cout, which would be quite small. Assuming the maximum parasitic is 0.2pF, and then we can find Rout as Ω=××××= − KRout 99.1)102.01042/(1 128pi , so choose Rout =1 .5K
. 2) Calculation of the source degeneration resistance  Because we need 14dB between adjacent coarse tuning steps, which corresponds to 5 times of amplification, we can calculate the maximum transconductance of input stage as mGdBKG mm 8.16 126425.15 max,max, ===×× Then connect the source degeneration resistor to get a 14dB lower gain than the maximum gain. From equation 4.5 103 Ω=Ω= Ω=Ω= Ω≈Ω≈ == + == + + = 450 ,300 9002 ,6002 900 ,600 and // Also 5.01 4.1 5 8.16 5.01 )/1( 22 22 spsn spsn spsn mpspmnsnpnmpmn mnsn mn mnsn npmn m RR RR RR gRgRgg gR gm gR g G µµ µµ (B.1) Finally for the last coarse tuning steps, another 14dB gain reduction is needed. ,5.4 ,3 4.52 ,6.32 4.5 ,6.3 and // Also 5.01 4.1 55 8.16 5.01 )/1( 11 1212 Ω=Ω= Ω=+Ω=+ Ω≈Ω≈ == + = × = + + = KRKR KRRKRR KRKR gRgRgg gR gm gR g G spsn spspsnsn spsn mpspmnsnpnmpmn mnsn mn mnsn npmn m µµ µµ (B.2) 3) Calculation of the dimensions and bias current of the input stage Because we adapt Approach II as mentioned previously to choose the same dimensions for both differential pairs, the overall transconductance is given by ( ) n mn n npmn m N g N g G + = + + = 1 4.1 1 /1 µµ (B.3) For the maximum gain setting, equation Gm reduces into mgmggG mnmn n p mnm 12 8.164.11 ===

      += µ µ To further calculate the dimension and bias current of the input stage, we have to determine VDSAT, Mn, VDSAT, Mp. And this has to meet three different cases VDSAT requirements, a) high gain range (28 ~ 42dB), b) middle gain range (14 ~ 26dB), and c) low gain range (0 ~ 12dB). 104 a) 28 ~ 42dB To accommodate the 1Vpp differential output signal requirement, with 28dB gain, it corresponds to a 39.9mVpp input signal. So in this case, we have to make VDSAT >40mV. b) 14 ~ 26dB With 14dB gain, 1Vpp differential output signal corresponds to a 200mVpp input signal. As the source degeneration resistor is included, which relaxes VDSAT by (1+N) times, N = 4, so the VDSAT requirement will be 200mVpp/(1+4) = 40mV. c) 0 ~ 12dB With 0dB gain, the required output signal corresponds to a 1Vpp input signal. With source degeneration, N = 24 in this case, so the VDSAT requirement will be 1Vpp/(1+24) = 40mV Overall, from the above three cases, with some margin, we set VDSAT,Mn= 150mV uAImVVmVIg biasMnDSATMnDSATbiasmn 400150 ,12/2 ,, ==== ( ) 2 , /232 gy, technoloIBM6HPfor ,/ because Also VuACVLWCg OXnMnDSATnOXnmn ≈= µµ ( ) ( ) umWW umLLWLW pn pn 78 24.0 ,345// == === 4) Calculation of the Dimensions of the Programmable Current Mirror Because the VGA is needed to handle a 1Vpp differential output signal, the single-ended signal at the output will be 0.5Vpp. With 1.5K load resistor, the AC current 105 at output will be 0.5/1500 = 0.33mA. As a rule of thumb, to accommodate this AC current, we must have 3 times larger DC current, which is 1mA. With maximum current gain of 5, the single ended DC current at the input of the current mirror will be 1mA/5 =0.2mA. Choose 220µA to leave some margin. For the VDSAT of the current mirrors, choose VDSAT = 150mV to prevent linearity degradation from the current mirror stage. Now we can calculate the dimensions of the current mirrors ( ) ( ) ( ) umWW umLLWLW VuAC VLWCI mVVuAI pn pn OXn MnDSATnOXnbias DSATbias 24 24.0 ,100// /232 ,Technology 0.25um 6HPIBMfor / 2 1 150 ,220 2 2 , == === ≈ = == µ µ The dimensions of the programmable current mirror are given in Table B.1. 106 Table B.1 Dimension of the bias circuits N 1.01 1.05 1.2 1.4 1.8 3 5.6 Current Gain (dB) 14 12 10 8 6 4 2 Wb (W1=24µm) 23.6 21.6 16.8 12 7.2 2.4 0.72 Mb1 Mb2 Mb3 Mb4 Mb5 Mb6 Mb7 W 2 µm 4.8 µm 4.8 µm 4.8 µm 4.8 µm 1.68 µm 0.72 µm L 0.24 µm At the end, we can roughly calculate the power consumption of this VGA. 107 VITA Lin Chen Texas Instruments, MS 8749 12500 TI Blvd, Dallas, Texas 75243 Education M.E. in Mechanical Engineering, Cornell University, Ithaca, New York, May 2001 B.E. in Automotive Engineering, Tsinghua University, Beijing, China, July 2000