Điều khiển và nhận dạng tiếng nói dùng DSP56002

— ns 244 Last DSCK Low of Read Register to First DSCK High of Next Command 7TC + 10 — ns 245 Last DSCK Low to DSO Invalid (Hold) 3 — ns 246 DR Assertion to second CKOUT transition for Wake Up from Wait state 12 TC ns 247 Second CKOUT transition to DSO after Wake Up from Wait state 17TC — ns 248 DR Assertion Width • To recover from Wait state • To recover from Wait state and enter Debug mode 15 13TC + 15 12TC – 15 — ns 249 DR Assertion to DSO (ACK) Valid (enter Debug mode) After Asynchronous Recovery from Wait State 17TC — ns 250A DR Assertion Width to Recover from Stop state1 • Stable External Clock, OMR Bit 6 = 0 • Stable External Clock, OMR Bit 6 = 1 • Stable External Clock, PCTL Bit 17= 1 15 15 15 65548TC + TL 20TC + TL 13TC + TL ns ns ns 2-36 DSP56002/D, Rev. 3 MOTOROLA Specifications OnCE Port Timing250B DR Assertion Width to Recover from Stop state and enter Debug mode1 • Stable External Clock,OMR Bit 6 = 0 • Stable External Clock,OMR Bit 6 = 1 • Stable External Clock,PCTL Bit 17= 1 65549TC + TL 21TC + TL 14TC + TL — — — ns ns ns 251 DR Assertion to DSO (ACK) Valid (enter Debug mode) after recovery from Stop state1 • Stable External Clock, OMR Bit 6 = 0 • Stable External Clock, OMR Bit 6 = 1 • Stable External Clock, PCTL Bit 17= 1 65553TC + TL 25TC + TL 18TC + TL — — — ns ns ns Notes: 1. A clock stabilization delay is required when using the on-chip crystal oscillator in two cases: • after power-on Reset, and • when recovering from Stop mode. During this stabilization period, TC, TH, and TL will not be constant. Since this stabilization period varies, a delay of 75,000 · TC is typically allowed to assure that the oscillator is stable before executing programs. While it is possible to set OMR bit 6 = 1 when using the internal crystal oscillator, it is not recommended and these specifications do not guarantee timings for that case. 2. The maximum specified is periodically sampled and not 100% tested. Figure 2-27 OnCE Serial Clock Timing Figure 2-28 OnCE Acknowledge Timing Table 2-15 OnCE Port Timing Num Characteristics Min Max Unit DSCK (Input) 230 231 232 AA0399 DR (Input) DSO (Output) (ACK) 233 AA0400 MOTOROLA DSP56002/D, Rev. 3 2-37 Specifications OnCE Port Timing Figure 2-29 OnCE Data I/O To Status Timing Figure 2-30 OnCE Read Timing Figure 2-31 OnCE Data I/O To Status Timing Note: High Impedance, external pull-down resistor DSCK (Input) DSO (Output) (ACK) (OS1) DSI (Input) (OS0) (See Note) (Last) 236 237 238 AA0501 Note: High Impedance, external pull-down resistor DSCK (Input) DSO (Output) (See Note) (Last) 234 235 245 AA0502 Note: High Impedance, external pull-down resistor (DSCK Input) (DSO Output) (DSI Input) OS1(Output) DSO (Output) OS0 (Output) (See Note) (See Note) 239 241 240 241 236 237 AA0503 2-38 DSP56002/D, Rev. 3 MOTOROLA Specifications OnCE Port Timing Figure 2-32 OnCE CKOUT To Status Timing Figure 2-33 OnCE Read Register to Next Command Timing Figure 2-34 Synchronous Recovery from Wait State Figure 2-35 Asynchronous Recovery from Wait State Note: High Impedance, external pull-down resistor CKOUT OS0–OS1 (Output) (See Note) 242 243 AA0504 DSCK (Input) (Next Command) 244 AA0505 T0, T2 T1, T3CKOUT DR (Input) DSO (Output) 248 246 247 AA0506 DR (Input) DSO (Output) 248 249 AA0507 MOTOROLA DSP56002/D, Rev. 3 2-39 Specifications OnCE Port TimingFigure 2-36 Asynchronous Recovery from Stop State DR (Input) DSO (Output) 250 251 AA0508 2-40 DSP56002/D, Rev. 3 MOTOROLA Specifications Timer TimingTIMER TIMING CL = 50 pF + 2 TTL loads Table 2-16 Timer Timing Num Characteristics Min Max Unit 260 TIO Low 2TC + 7 — ns 261 TIO High 2TC + 7 — ns 262 Synchronous Timer Setup Time from TIO (input) Assertion to CKOUT Rising Edge 10 TC ns 263 Synchronous Timer Delay Time from CKOUT Rising Edge to the External Memory Access Address Out Valid Caused by First Interrupt Instruction Execution 5TC + TH — ns 264 CKOUT Rising Edge to TIO (output) Assertion 0 8 ns 265 CKOUT Rising Edge to TIO (output) Deassertion 0 8 ns 266 CKOUT Rising Edge to TIO (General Purpose Output) 0 8 ns Figure 2-37 TIO Timer Event Input Figure 2-38 Timer Interrupt Generation TIO 261260 AA0509 CKOUT TIO (Input) First Interrupt Instruction Execution ADDRESS 262 263 AA0510 MOTOROLA DSP56002/D, Rev. 3 2-41 Specifications Timer TimingFigure 2-39 External Pulse Generation Figure 2-40 GPIO Output Timing CKOUT TIO (Output) 264 265 AA0511 CKOUT TIO (Output) A0–A15 fetch the instruction MOVE X0,X:(R0); X0 contains the new value of TIO ; and R0 contains the address of TCSR EXTP, X/Y PS, DS 266 AA0512 2-42 DSP56002/D, Rev. 3 MOTOROLA SECTION 3 PACKAGING PIN-OUT AND PACKAGE INFORMATION This sections provides information about the available packages for this product, including diagrams of the package pinouts and tables describing how the signals described in Section 1 are allocated for each package. The DSP56002 is available in three package types: • 132-pin Plastic Quad Flat Pack (PQFP) • 144-pin Thin Quad Flat Pack (TQFP) • 132-pin Ceramic Pin Grid Array (PGA) MOTOROLA DSP56002/D, Rev. 3 3-1 Packaging Pin-out and Package Information PQFP Package Description Top and bottom views of the PQFP package are shown in Figure 3-1 and Figure 3-2 with their pin-outs. Figure 3-1 Top View of the 132-pin Plastic Quad Flat Pack (PQFP) Package Note: 1. “NC” are No Connection pins that are reserved for possible future enhancements. Do not connect these pins to any power, ground, signal traces, or vias. 2. An OVERBAR indicates the signal is asserted when the voltage = ground (active low). 3. To simplify locating the pins, each fifth pin is shaded in the illustration. Orientation Mark 1 84 51 (Chamfered Edge) 18 11 7 (Top View) H4/PB4 H3/PB3 VCCH H2/PB2 GNDH H1/PB1 H0/PB0 RXD/PC0 TXD/PC1 GNDS SCLK/PC2 SC0/PC3 VCCS SCK/PC6 SC2/PC5 STD/PC8 GNDS SC1/PC4 GNDQ VCCQ SRD/PC7 TIO NC BN WT BG BR VCCC WR RD GNDC NC DSCK/OS1 GNDD D21 D20 VCCD D19 D18 GNDD D17 D16 D15 D14 GNDD D13 D12 VCCD D11 D10 GNDD GNDQ VCCQ D9 D8 D7 D6 GNDD D5 D4 VCCD D3 D2 GNDD D1 D0 H 5/ PB 5 G ND H H 6/ PB 6 H 7/ PB 7 H R EQ /P B1 3 H R /W /P B1 1 G ND H H EN /P B1 2 V C CH H AC K/ PB 14 H A0 /P B8 H A1 /P B9 G ND H H A2 /P B1 0 G ND Q V C CQ EX TA L XT AL PI N IT PL O CK G ND P PC AP V C CP CK P R ES ET V C CC K CK O UT G ND CK M O DA /IR QA M O DB /IR QB M O DC /N M I D 23 D 22 D R D SO D SI /O S0 BS X/ Y G ND A D S V C CA PS A 0 A1 G ND A A2 A3 A4 V C CQ G ND Q A5 V C CA G ND A A6 A7 A8 A9 G ND A A1 0 A1 1 A1 2 V C CA A1 3 G ND A A1 4 A1 5 AA0611 3-2 DSP56002/D, Rev. 3 MOTOROLA Packaging Pin-out and Package Information Figure 3-2 Bottom View of the 132-pin Plastic Quad Flat Pack (PQFP) Package Note: 1. “NC” are No Connection pins that are reserved for possible future enhancements. Do not connect these pins to any power, ground, signal traces, or vias. 2. An OVERBAR indicates the signal is asserted when the voltage = ground (active low). 3. To simplify locating the pins, each fifth pin is shaded in the illustration. Orientation Mark 1 84 51 (Chamfered Edge 18 11 7 (Bottom View) H4/PB4 H3/PB3 VCCH H2/PB2 GNDH H1/PB1 H0/PB0 RXD/PC0 TXD/PC1 GNDS SCLK/PC2 SC0/PC3 VCCS SCK/PC6 SC2/PC5 STD/PC8 GNDS SC1/PC4 GNDQ VCCQ SRD/PC7 TIO NC BN WT BG BR VCCC WR RD GNDC NC DSCK/OS1 GNDD D21 D20 VCCD D19 D18 GNDD D17 D16 D15 D14 GNDD D13 D12 VCCD D11 D10 GNDD GNDQ VCCQ D9 D8 D7 D6 GNDD D5 D4 VCCD D3 D2 GNDD D1 D0 H 5/ PB 5 G ND H H 6/ PB 6 H 7/ PB 7 H R EQ /P B1 3 H R /W /P B1 1 G ND H H EN /P B1 2 V C CH H AC K/ PB 14 H A0 /P B8 H A1 /P B9 G ND H H A2 /P B1 0 G ND Q V C CQ EX TA L XT AL PI N IT PL O CK G ND P PC AP V C CP CK P R ES ET V C CC K CK O UT G ND CK M O DA /IR QA M O DB /IR QB M O DC /N M I D 23 D 22 D R D SO D SI /O S0BSX/ Y G ND AD S V C CAPSA 0A1 G ND AA2A3A4 V C CQ G ND QA5 V C CA G ND AA6A7A8A9 G ND A A1 0 A1 1 A1 2 V C CAA1 3 G ND A A1 4 A1 5 AA0612 on Top Side) MOTOROLA DSP56002/D, Rev. 3 3-3 Packaging Pin-out and Package Information The DSP56002 signals that may be programmed as General Purpose I/O are listed with their primary function in Table 3-9. Table 3-1 DSP56002 General Purpose I/O Pin Identification in PQFP Package Pin Number Primary Function Port GPIO ID 24 H0 B PB0 23 H1 PB1 21 H2 PB2 19 H3 PB3 18 H4 PB4 17 H5 PB5 15 H6 PB6 14 H7 PB7 7 HA0 PB8 6 HA1 PB9 4 HA2 PB10 12 HR/W PB11 10 HEN PB12 13 HREQ PB13 8 HACK PB14 25 RXD C PC0 26 TXD PC1 28 SCLK PC2 29 SC0 PC3 35 SC1 PC4 32 SC2 PC5 31 SCK PC6 38 SRD PC7 33 STD PC8 39 TIO No port assigned 3-4 DSP56002/D, Rev. 3 MOTOROLA Packaging Pin-out and Package Information Table 3-2 DSP56002 Signal Identification by PQFP Pin Number Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name 1 EXTAL 26 TXD/PC1 51 DR 2 VCCQ 27 GNDS 52 DSO 3 GNDQ 28 SCLK/PC2 53 DSI/OS0 4 HA2/PB10 29 SC0/PC3 54 BS 5 GNDH 30 VCCS 55 X/Y 6 HA1/PB9 31 SCK/PC6 56 GNDA 7 HA0/PB8 32 SC2/PC5 57 DS 8 HACK/PB14 33 STD/PC8 58 VCCA 9 VCCH 34 GNDS 59 PS 10 HEN/PB12 35 SC1/PC4 60 A0 11 GNDH 36 GNDQ 61 A1 12 HR/W/PB11 37 VCCQ 62 GNDA 13 HREQ/PB13 38 SRD/PC7 63 A2 14 H7/PB7 39 TIO* 64 A3 15 H6/PB6 40 NC 65 A4 16 GNDH 41 BN 66 VCCQ 17 H5/PB5 42 WT 67 GNDQ 18 H4/PB4 43 BG 68 A5 19 H3/PB3 44 BR 69 VCCA 20 VCCH 45 VCCC 70 GNDA 21 H2/PB2 46 WR 71 A6 22 GNDH 47 RD 72 A7 23 H1/PB1 48 GNDC 73 A8 24 H0/PB0 49 NC 74 A9 25 RXD/PC0 50 DSCK/OS1 75 GNDA MOTOROLA DSP56002/D, Rev. 3 3-5 Packaging Pin-out and Package Information76 A10 95 D8 114 D20 77 A11 96 D9 115 D21 78 A12 97 VCCQ 116 GNDD 79 VCCA 98 GNDQ 117 D22 80 A13 99 GNDD 118 D23 81 GNDA 100 D10 119 MODC/NMI 82 A14 101 D11 120 MODB/IRQB 83 A15 102 VCCD 121 MODA/IRQA 84 D0 103 D12 122 GNDCK 85 D1 104 D13 123 CKOUT 86 GNDD 105 GNDD 124 VCCCK 87 D2 106 D14 125 RESET 88 D3 107 D15 126 CKP 89 VCCD 108 D16 127 VCCP 90 D4 109 D17 128 PCAP 91 D5 110 GNDD 129 GNDP 92 GNDD 111 D18 130 PLOCK 93 D6 112 D19 131 PINIT 94 D7 113 VCCD 132 XTAL Note: 1. “NC” are No Connection pins that are reserved for possible future enhancements. Do not connect these pins to any power, ground, signal traces, or vias. 2. An OVERBAR indicates the signal is asserted when the voltage = ground (active low). Table 3-2 DSP56002 Signal Identification by PQFP Pin Number (Continued) Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name 3-6 DSP56002/D, Rev. 3 MOTOROLA Packaging Pin-out and Package InformationTable 3-3 DSP56002 PQFP Pin Identification by Signal Name Signal Name Pin No. Signal Name Pin No. Signal Name Pin No. A0 60 D3 114 DSO 52 A1 61 D4 116 EXTAL 1 A2 63 D5 117 GNDA 56 A3 64 D6 119 GNDA 62 A4 65 D7 94 GNDA 70 A5 68 D8 95 GNDA 75 A6 71 D9 96 GNDA 81 A7 72 D10 100 GNDC 48 A8 73 D11 101 GNDCK 122 A9 74 D12 103 GNDD 86 A10 76 D13 104 GNDD 92 A11 77 D14 106 GNDD 99 A12 78 D15 107 GNDD 105 A13 80 D16 108 GNDD 110 A14 82 D17 109 GNDD 116 A15 83 D18 111 GNDH 5 BG 43 D19 112 GNDH 11 BN 41 D20 114 GNDH 16 BR 44 D21 115 GNDH 22 BS 54 D22 117 GNDP 129 CKOUT 123 D23 118 GNDQ 3 CKP 126 DR 51 GNDQ 36 D0 84 DS 57 GNDQ 67 D1 85 DSCK 50 GNDQ 98 D2 87 DSI 53 GNDS 27 MOTOROLA DSP56002/D, Rev. 3 3-7 Packaging Pin-out and Package InformationGNDS 34 PB1 23 PLOCK 130 H0 24 PB2 21 PS 59 H1 23 PB3 19 RD 47 H2 21 PB4 18 RESET 125 H3 19 PB5 17 RXD 25 H4 18 PB6 15 SC0 29 H5 17 PB7 14 SC1 35 H6 15 PB8 7 SC2 32 H7 14 PB9 6 SCK 31 HA0 7 PB10 4 SCLK 28 HA1 6 PB11 12 SRD 38 HA2 4 PB12 10 STD 33 HACK 8 PB13 13 TIO 39 HEN 10 PB14 8 TXD 26 HR/W 12 PC0 25 VCCA 58 HREQ 13 PC1 26 VCCA 69 IRQA 121 PC2 28 VCCA 79 IRQB 120 PC3 29 VCCC 45 MODA 121 PC4 35 VCCCK 124 MODB 120 PC5 32 VCCD 89 MODC 119 PC6 31 VCCD 102 NMI 119 PC7 38 VCCD 113 OS0 53 PC8 33 VCCH 9 OS1 50 PCAP 128 VCCH 20 PB0 24 PINIT 131 VCCP 127 VCCQ 2 VCCS 30 XTAL 132 VCCQ 37 WR 46 nc 40 VCCQ 66 WT 42 nc 49 VCCQ 97 X/Y 55 Table 3-3 DSP56002 PQFP Pin Identification by Signal Name (Continued) Signal Name Pin No. Signal Name Pin No. Signal Name Pin No. 3-8 DSP56002/D, Rev. 3 MOTOROLA Packaging Pin-out and Package InformationPower and ground pins have special considerations for noise immunity. See Section 4 Design Considerations. Table 3-4 DSP56002 Power Supply Pins in PQFP Package Pin Number Power Supply Circuit Supplied 58 VCCA Address Bus Buffers 69 79 56 GNDA 62 70 75 81 45 VCCC Bus Control Buffers48 GNDC 124 VCCCK Clock 122 GNDCK 89 VCCD Data Bus Buffers 102 113 86 GNDD 92 99 105 110 116 9 VCCH Host Interface Buffers 20 5 GNDH 11 16 22 MOTOROLA DSP56002/D, Rev. 3 3-9 Packaging Pin-out and Package Information2 VCCQ Internal Logic 37 66 97 3 GNDQ 36 67 98 127 VCCP PLL 129 GNDP 30 VCCS Serial Port27 GNDS34 Table 3-4 DSP56002 Power Supply Pins in PQFP Package (Continued) Pin Number Power Supply Circuit Supplied 3-10 DSP56002/D, Rev. 3 MOTOROLA Packaging Pin-out and Package InformationFigure 3-3 132-Pin Plastic Quad Flat Pack (PQFP) Mechanical Information L L-M0.016 NH A1 S J A S1 J11 17 117 18 116 50 84 51 83 VIEW AB PIN 1 IDENT AA AA V1 B1 P V B P1 2X0.002 L-M 4X 2X0.002 N 4X 0.004 T C1 4X 33 TIPS C2C SEATING PLANE D1132X GAGE PLANE AC AC 128X G X=L, M, OR N CL VIEW AB (D) BASE D2 E E1 PLATING SECTION AC-AC KD132X U W q L-MM0.008 NT R R1 M N L-M0.010 NT L-M0.012 NH T 132X L-MM0.008 NT H K1 X SECTION AA-AA DIM MIN MAX INCHES A 1.100 BSC A1 0.550 BSC B 1.100 BSC B1 0.550 BSC C 0.160 0.180 C1 0.020 0.040 C2 0.135 0.145 D 0.008 0.012 D1 0.012 0.016 D2 0.008 0.011 E 0.006 0.008 E1 0.005 0.007 F 0.014 0.014 G 0.025 BSC J 0.950 BSC J1 0.475 BSC K 0.034 0.044 K1 0.010 BSC P 0.950 BSC P1 0.475 BSC S 1.080 BSC S1 0.540 BSC U 0.025 REF V 1.080 BSC V1 0.540 BSC W 0.006 0.008 q 0 žž° 8 ° R1 0.013 REF METAL NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1982. 2. DIMENSIONS IN INCHES. 3. DIMENSIONS A, B, J, AND P DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTRUSION FOR DIMENSIONS A AND B IS 0.007, FOR DIMENSIONS J AND P IS 0.010. 4. DATUM PLANE H IS LOCATED AT THE UNDERSIDE OF LEADS WHERE LEADS EXIT PACKAGE BODY. 5. DATUMS L, M, AND N TO BE DETERMINED WHERE CENTER LEADS EXIT PACKAGE BODY AT DATUM H. 6. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE, DATUM T. 7. DIMENSIONS A, B, J, AND P TO BE DETERMINED AT DATUM PLANE H. 8. DIMENSION F DOES NOT INCLUDE DAMBAR PROTRUSIONS. DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.019. CASE 831A-02 ISSUE C MOTOROLA DSP56002/D, Rev. 3 3-11 Packaging Pin-out and Package InformationTQFP Package Description Top and bottom views of the TQFP package are shown in Figure 3-4 and Figure 3-5 with their pin-outs. Figure 3-4 Top View of the 144-pin Thin Quad Flat Pack (TQFP) Package Note: 1. “NC” are No Connection pins that are reserved for possible future enhancements. Do not connect these pins to any power, ground, signal traces, or vias. 2. An OVERBAR indicates the signal is asserted when the voltage = ground (active low). 3. To simplify locating the pins, each fifth pin is shaded in the illustration. Orientation Mark 109 1 37 73NC D0 D1 GNDD D2 D3 VCCD D4 D5 GNDD D6 D7 D8 D9 VCCQ GNDQ GNDD D10 NC D11 VCCD D12 D13 GNDD D14 D15 D16 D17 GNDD D18 D19 VCCD D20 D21 GNDD NC NC DSCK/OS1 NC GNDC RD WR VCCC BR BG WT BN NC TIO SRD/PC7 VCCQ GNDQ SC1/PC4 NC GNDS STD/PC8 SC2/PC5 SCK/PC6 VCCS SC0/PC3 SCLK/PC2 GNDS TXD/PC1 RXD/PC0 H0/PB0 H1/PB1 GNDH H2/PB2 VCCH H3/PB3 H4/PB4 NC N C D 22 D 23 M O DC /N M I M O DB /IR QB M O DA /IR QA G ND CK CK O UT V C CC K R ES ET CK P V C CP PC AP G ND P PL O CK PI N IT XT AL N C EX TA L V C CQ G ND Q H A2 /P B1 0 G ND H H A1 /P B9 H A0 /P B8 H AC K/ PB 14 V C CH H EN /P B1 2 G ND H H R /W /P B1 1 H R EQ /P B1 3 H 7/ PB 7 H 6/ PB 6 G ND H H 5/ PB 5 N C N C A1 5 A1 4 G ND A A1 3 V C CA A1 2 A1 1 A1 0 G ND A A9 A8 A7 A6 G ND A V C CA A5 N C G ND Q V C CQ A4 A3 A2 G ND A A1 A0 PS V C CA D S G ND A X/ Y BS DS I/O S0 D SO D R N C AA0613 (Top View) 3-12 DSP56002/D, Rev. 3 MOTOROLA Packaging Pin-out and Package InformationFigure 3-5 Bottom View of the144-pin Thin Quad Flat Pack (TQFP) Package Note: 1. “NC” are No Connection pins that are reserved for possible future enhancements. Do not connect these pins to any power, ground, signal traces, or vias. 2. An OVERBAR indicates the signal is asserted when the voltage = ground (active low). 3. To simplify locating the pins, each fifth pin is shaded in the illustration. Orientation Mark 109 137 73 NC D0 D1 GNDD D2 D3 VCCD D4 D5 GNDD D6 D7 D8 D9 VCCQ GNDQ GNDD D10 NC D11 VCCD D12 D13 GNDD D14 D15 D16 D17 GNDD D18 D19 VCCD D20 D21 GNDD NC NC DSCK/OS1 NC GNDC RD WR VCCC BR BG WT BN NC TIO SRD/PC7 VCCQ GNDQ SC1/PC4 NC GNDS STD/PC8 SC2/PC5 SCK/PC6 VCCS SC0/PC3 SCLK/PC2 GNDS TXD/PC1 RXD/PC0 H0/PB0 H1/PB1 GNDH H2/PB2 VCCH H3/PB3 H4/PB4 NC N C D 22 D 23 M O DC /N M I M O DB /IR QB M O DA /IR QA G ND CK CK O UT V C CC K R ES ET CK P V C CP PC AP G ND P PL O CK PI N IT XT ALN C EX TA L V C CQ G ND Q H A2 /P B1 0 G ND H H A1 /P B9 H A0 /P B8 H AC K/ PB 14 V C CH H EN /P B1 2 G ND H H R /W /P B1 1 H R EQ /P B1 3 H 7/ PB 7 H 6/ PB 6 G ND H H 5/ PB 5 N C N C A1 5 A1 4 G ND A A1 3 V C CA A1 2 A1 1 A1 0 G ND A A9A8A7A6G ND A V C CA A5N CG ND Q V C CQ A4A3A2G ND A A1A0PSV C CA D SG ND A X/ Y BSDS I/O S0 D SO D R N C AA0614 (Bottom View) (on Top Side) MOTOROLA DSP56002/D, Rev. 3 3-13 Packaging Pin-out and Package InformationThe DSP56002 signals that may be programmed as General Purpose I/O are listed with their primary function in Table 3-9. Table 3-5 DSP56002 General Purpose I/O Pin Identification in TQFP Package Pin Number Primary Function Port GPIO ID 44 H0 B PB0 43 H1 PB1 41 H2 PB2 39 H3 PB3 38 H4 PB4 35 H5 PB5 33 H6 PB6 32 H7 PB7 25 HA0 PB8 24 HA1 PB9 22 HA2 PB10 30 HR/W PB11 28 HEN PB12 31 HREQ PB13 26 HACK PB14 45 RXD C PC0 46 TXD PC1 48 SCLK PC2 49 SC0 PC3 56 SC1 PC4 52 SC2 PC5 51 SCK PC6 59 SRD PC7 53 STD PC8 60 TIO No port assigned 3-14 DSP56002/D, Rev. 3 MOTOROLA Packaging Pin-out and Package InformationTable 3-6 DSP56002 Signal Identification by TQFP Pin Number Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name 1 NC 26 HACK/PB14 51 SCK/PC6 2 D22 27 VCCH 52 SC2/PC5 3 D23 28 HEN/PB12 53 STD/PC8 4 MODC/NMI 29 GNDH 54 GNDS 5 MODB/IRQB 30 HR/W/PB11 55 NC 6 MODA/IRQA 31 HREQ/PB13 56 SC1/PC4 7 GNDCK 32 H7/PB7 57 GNDQ 8 CKOUT 33 H6/PB6 58 VCCQ 9 VCCCK 34 GNDH 59 SRD/PC7 10 RESET 35 H5/PB5 60 TIO 11 CKP 36 NC 61 NC 12 VCCP 37 NC 62 BN 13 PCAP 38 H4/PB4 63 WT 14 GNDP 39 H3/PB3 64 BG 15 PLOCK 40 VCCH 65 BR 16 PINIT 41 H2/PB2 66 VCCC 17 XTAL 42 GNDH 67 WR 18 NC 43 H1/PB1 68 RD 19 EXTAL 44 H0/PB0 69 GNDC 20 VCCQ 45 RXD/PC0 70 NC 21 GNDQ 46 TXD/PC1 71 DSCK/OS1 22 HA2/PB10 47 GNDS 72 NC 23 GNDH 48 SCLK/PC2 73 NC 24 HA1/PB9 49 SC0/PC3 74 DR 25 HA0/PB8 50 VCCS 75 DSO MOTOROLA DSP56002/D, Rev. 3 3-15 Packaging Pin-out and Package Information76 DSI/OS0 99 GNDA 122 D9 77 BS 100 A10 123 VCCQ 78 X/Y 101 A11 124 GNDQ 79 GNDA 102 A12 125 GNDD 80 DS 103 VCCA 126 D10 81 VCCA 104 A13 127 NC 82 PS 105 GNDA 128 D11 83 A0 106 A14 129 VCCD 84 A1 107 A15 130 D12 85 GNDA 108 NC 131 D13 86 A2 109 NC 132 GNDD 87 A3 110 D0 133 D14 88 A4 111 D1 134 D15 89 VCCQ 112 GNDD 135 D16 90 GNDQ 113 D2 136 D17 91 NC 114 D3 137 GNDD 92 A5 115 VCCD 138 D18 93 VCCA 116 D4 139 D19 94 GNDA 117 D5 140 VCCD 95 A6 118 GNDD 141 D20 96 A7 119 D6 142 D21 97 A8 120 D7 143 GNDD 98 A9 121 D8 144 NC Note: 1. “NC” are No Connection pins that are reserved for possible future enhancements. Do not connect these pins to any power, ground, signal traces, or vias. 2. An OVERBAR indicates the signal is asserted when the voltage = ground (active low). Table 3-6 DSP56002 Signal Identification by TQFP Pin Number (Continued) Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name 3-16 DSP56002/D, Rev. 3 MOTOROLA Packaging Pin-out and Package InformationTable 3-7 DSP56002 TQFP Pin Identification by Signal Name Signal Name Pin No. Signal Name Pin No. Signal Name Pin No. A0 83 D3 114 DSO 75 A1 84 D4 116 EXTAL 19 A2 86 D5 117 GNDA 79 A3 87 D6 119 GNDA 85 A4 88 D7 120 GNDA 94 A5 92 D8 121 GNDA 99 A6 95 D9 122 GNDA 105 A7 96 D10 126 GNDC 69 A8 97 D11 128 GNDCK 7 A9 98 D12 130 GNDD 112 A10 100 D13 131 GNDD 118 A11 101 D14 133 GNDD 125 A12 102 D15 134 GNDD 132 A13 104 D16 135 GNDD 137 A14 106 D17 136 GNDD 143 A15 107 D18 138 GNDH 23 BG 64 D19 139 GNDH 29 BN 62 D20 141 GNDH 34 BR 65 D21 142 GNDH 42 BS 77 D22 2 GNDP 14 CKOUT 8 D23 3 GNDQ 21 CKP 11 DR 74 GNDQ 57 D0 110 DS 80 GNDQ 90 D1 111 DSCK 71 GNDQ 124 D2 113 DSI 76 GNDS 47 MOTOROLA DSP56002/D, Rev. 3 3-17 Packaging Pin-out and Package InformationGNDS 54 PB1 43 PLOCK 15 H0 44 PB2 41 PS 82 H1 43 PB3 39 RD 68 H2 41 PB4 38 RESET 10 H3 39 PB5 35 RXD 45 H4 38 PB6 33 SC0 49 H5 35 PB7 32 SC1 56 H6 33 PB8 25 SC2 52 H7 32 PB9 24 SCK 51 HA0 25 PB10 22 SCLK 48 HA1 24 PB11 30 SRD 59 HA2 22 PB12 28 STD 53 HACK 26 PB13 31 TIO 60 HEN 28 PB14 26 TXD 46 HR/W 30 PC0 45 VCCA 81 HREQ 31 PC1 46 VCCA 93 IRQA 6 PC2 48 VCCA 103 IRQB 5 PC3 49 VCCC 66 MODA 6 PC4 56 VCCCK 9 MODB 5 PC5 52 VCCD 115 MODC 4 PC6 51 VCCD 129 NMI 4 PC7 59 VCCD 140 OS0 76 PC8 53 VCCH 27 OS1 71 PCAP 13 VCCH 40 PB0 44 PINIT 16 VCCP 12 Table 3-7 DSP56002 TQFP Pin Identification by Signal Name (Continued) Signal Name Pin No. Signal Name Pin No. Signal Name Pin No. 3-18 DSP56002/D, Rev. 3 MOTOROLA Packaging Pin-out and Package InformationVCCQ 20 XTAL 17 nc 72 VCCQ 58 nc 70 nc 73 VCCQ 89 nc 1 nc 91 VCCQ 123 nc 18 nc 108 VCCS 50 nc 36 nc 109 WR 67 nc 37 nc 127 WT 63 nc 55 nc 144 X/Y 78 nc 61 Table 3-7 DSP56002 TQFP Pin Identification by Signal Name (Continued) Signal Name Pin No. Signal Name Pin No. Signal Name Pin No. MOTOROLA DSP56002/D, Rev. 3 3-19 Packaging Pin-out and Package InformationPower and ground pins have special considerations for noise immunity. See the section Design Considerations. Table 3-8 DSP56002 Power Supply Pins in TQFP Package Pin Number Power Supply Circuit Supplied 81 VCCA Address Bus Buffers 93 103 79 GNDA 85 94 99 105 66 VCCC Bus Control Buffers69 GNDC 9 VCCCK Clock 7 GNDCK 115 VCCD Data Bus Buffers 129 140 112 GNDD 118 125 132 137 143 27 VCCH Host Interface Buffers 40 23 GNDH 29 34 42 3-20 DSP56002/D, Rev. 3 MOTOROLA Packaging Pin-out and Package Information20 VCCQ Internal Logic 58 89 123 21 GNDQ 57 90 124 12 VCCP PLL 14 GNDP 50 VCCS Serial Port47 GNDS54 Table 3-8 DSP56002 Power Supply Pins in TQFP Package (Continued) Pin Number Power Supply Circuit Supplied MOTOROLA DSP56002/D, Rev. 3 3-21 Packaging Pin-out and Package InformationFigure 3-6 144-pin Thin Plastic Quad Flat Pack (TQFP) Mechanical Information SEATING PLANE 0.1 T 144XC 2q VIEW AB 2q T PLATING F AAJ D BASEMETAL SECTION J1-J1 (ROTATED 90) 144 PL M0.08 NT L-M N0.20 T L-M 144 73 109 37 1081 36 72 4X 4X 36 TIPS PIN 1 IDENT VIEW Y B B1 V1 A1 S1 V A S N0.20 T L-M ML N P4X G140X J1 J1 VIEW Y CL X X=L, M OR N GAGE PLANE q 0.05 (Z) R2 E C2 (Y) R1 (K) C1 1q 0.25 VIEW AB DIM MIN MAX MILLIMETERS A 20.00 BSC A1 10.00 BSC B 20.00 BSC B1 10.00 BSC C 1.40 1.60 C1 0.05 0.15 C2 1.35 1.45 D 0.17 0.27 E 0.45 0.75 F 0.17 0.23 G 0.50 BSC J 0.09 0.20 K 0.50 REF P 0.25 BSC R1 0.13 0.20 R2 0.13 0.20 S 22.00 BSC S1 11.00 BSC V 22.00 BSC V1 11.00 BSC Y 0.25 REF Z 1.00 REF AA 0.09 0.16 q 0 ° q 0° 7 ° q 11 ° 13 ° 1 2 NOTES: 9. DIMENSIONS AND TOLERANCING PER ASME Y14.5, 1994. 10.DIMENSIONS IN MILLIMETERS. 11.DATUMS L, M AND N TO BE DETERMINED AT THE SEATING PLANE, DATUM T. 12.DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE, DATUM T. 13.DIMENSIONS A AND B DO NOT INCULDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE H. 14.DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLED DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.35. CASE 918-03 — ISSUE C 3-22 DSP56002/D, Rev. 3 MOTOROLA Packaging Pin-out and Package InformationPGA Package Description Top and bottom views of the PGA package are shown in Figure 3-7 and Figure 3-8 with their pin-outs. Figure 3-7 Top View of the 132-pin Ceramic (RC) 13 · 13 Pin Grid Array Package Note: 1. “NC” are No Connection pins that are reserved for possible future enhancements. Do not connect these pins to any power, ground, signal traces, or vias. 2. An OVERBAR indicates the signal is asserted when the voltage = ground (active low). Orientation Mark A B C D E F G H J K L M N 1 2 3 4 5 6 7 8 9 10 11 12 13 GNDQ GNDD VCCD GNDD GNDD D15 D14 D11 VCCD GNDD GNDD VCCD GNDD GNDQ RESET D21 D19 D17 D12 D9 D7 D5 D3 D1 GNDA VCCQ CKP GNDCK D23 D22 A15 A14 A13 A12 VCCA GNDQ VCCP CKOUT MODC/ NMI A11 A10 A9 GNDA VCCQ PCAP GNDP A8 A7 GNDA GNDQ PLOCK PINIT A6 A5 VCCA VCCQ XTAL EXTAL A3 A4 GNDA HA2 HA1 HA0 HR/W A0 A1 A2 VCCA HACK HEN HREQ H4 H3 RD X/Y DS PS GNDA H6 H7 H2 H1 H0 SC0 STD TIO WR DR DSO DSI/OS0 BS GNDH H5 RXD TXD SCLK SCK SC1 NC WT BG BR NC DSCK/ OS1 GNDH VCCH GNDH VCCH GNDH SC2 SRD BN GNDS VCCS GNDS VCCC GNDC VCCQ VCCCK MODB/ IRQB D20 D18 D16 D13 D10 D8 D6 D4 D2 D0 MODA/ IRQA AA0615 Top View MOTOROLA DSP56002/D, Rev. 3 3-23 Packaging Pin-out and Package InformationFigure 3-8 Bottom View of the 132-pin Ceramic (RC) 13 · 13 Pin Grid Array Package Note: 1. “NC” are No Connection pins that are reserved for possible future enhancements. Do not connect these pins to any power, ground, signal traces, or vias. 2. An OVERBAR indicates the signal is asserted when the voltage = ground (active low). Orientation Mark (on Top Side) A B C D E F G H J K L M N 12345678910111213 GNDQ GNDD VCCD GNDD GNDD D15 D14 D11 VCCD GNDD GNDD VCCD GNDD GNDQ RESET D21 D19 D17 D12 D9 D7 D5 D3 D1 GNDA VCCQ CKP GNDCK D23 D22 A15 A14 A13 A12 VCCA GNDQ VCCP CKOUT MODC/ NMI A11 A10 A9 GNDA VCCQ PCAP GNDP A8 A7 GNDA GNDQ PLOCK PINIT A6 A5 VCCA VCCQ XTAL EXTAL A3 A4 GNDA HA2 HA1 HA0 HR/W A0 A1 A2 VCCA HACK HEN HREQ H4 H3 RD X/Y DS PS GNDA H6 H7 H2 H1 H0 SC0 STD TIO WR DR DSO DSI/OS0 BS GNDH H5 RXD TXD SCLK SCK SC1 NC WT BG BR NC DSCK/ OS1 GNDH VCCH GNDH VCCH GNDH SC2 SRD BN GNDS VCCS GNDS VCCC GNDC VCCQ VCCCK MODB/ IRQB D20 D18 D16 D13 D10 D8 D6 D4 D2 D0 MODA/ IRQA AA0616 Bottom View 3-24 DSP56002/D, Rev. 3 MOTOROLA Packaging Pin-out and Package InformationThe DSP56008 signals that may be programmed as General Purpose I/O are listed with their primary function in Table 3-9. Table 3-9 DSP56002 General Purpose I/O Pin Identification in PGA Package Pin Number Primary Function Port GPIO ID E11 H0 B PB0 D11 H1 PB1 C11 H2 PB2 E10 H3 PB3 D10 H4 PB4 B12 H5 PB5 A11 H6 PB6 B11 H7 PB7 C9 HA0 PB8 B9 HA1 PB9 A9 HA2 PB10 D9 HR/W PB11 B10 HEN PB12 C10 HREQ PB13 A10 HACK PB14 C12 RXD C PC0 D12 TXD PC1 E12 SCLK PC2 F11 SC0 PC3 G12 SC1 PC4 F13 SC2 PC5 F12 SCK PC6 G13 SRD PC7 G11 STD PC8 H11 TIO No port assigned MOTOROLA DSP56002/D, Rev. 3 3-25 Packaging Pin-out and Package InformationTable 3-10 DSP56002 Signal Identification by PGA Pin Number Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name A1 GNDQ B13 VCCH E2 D18 A2 VCCQ C1 VCCD E3 D19 A3 GNDQ C2 MODB/IRQB E4 D22 A4 VCCQ C3 MODA/IRQA E10 H3/PB3 A5 GNDQ C4 GNDCK E11 H0/PB0 A6 VCCQ C5 CKOUT E12 SCLK/PC2 A7 GNDQ C6 GNDP E13 GNDH A8 VCCQ C7 PINIT F1 D15 A9 HA2/PB10 C8 EXTAL F2 D16 A10 HACK/PB14 C9 HA0/PB8 F3 D17 A11 H6/PB6 C10 HREQ/PB13 F11 SC0/PC3 A12 GNDH C11 H2/PB2 F12 SCK/PC6 A13 GNDH C12 RXD/PC0 F13 SC2/PC5 B1 GNDD C13 GNDH G1 D14 B2 VCCCK D1 GNDD G2 D13 B3 RESET D2 D20 G3 D12 B4 CKP D3 D21 G11 STD/PC8 B5 VCCP D4 D23 G12 SC1/PC4 B6 PCAP D5 MODC/NMI G13 SRD/PC7 B7 PLOCK D9 HR/W/PB11 H1 D11 B8 XTAL D10 H4/PB4 H2 D10 B9 HA1/PB9 D11 H1/PB1 H3 D9 B10 HEN/PB12 D12 TXD/PC1 H11 TIO* B11 H7/PB7 D13 VCCH H12 NC B12 H5/PB5 E1 GNDD H13 BN 3-26 DSP56002/D, Rev. 3 MOTOROLA Packaging Pin-out and Package InformationJ1 VCCD L2 D4 M8 A4 J2 D8 L3 D3 M9 A2 J3 D7 L4 A13 M10 PS J4 A15 L5 A10 M11 DSI/OS0 J10 RD L6 A8 M12 NC J11 WR L7 A6 M13 VCCC J12 WT L8 A3 N1 GNDD J13 GNDS L9 A1 N2 D0 K1 GNDD L10 DS N3 GNDA K2 D6 L11 DSO N4 VCCA K3 D5 L12 BR N5 GNDA K4 A14 L13 GNDS N6 GNDA K5 A11 M1 VCCD N7 VCCA K9 A0 M2 D2 N8 GNDA K10 X/Y M3 D1 N9 VCCA K11 DR M4 A12 N10 GNDA K12 BG M5 A9 N11 BS K13 VCCS M6 A7 N12 DSCK/OS1 L1 GNDD M7 A5 N13 GNDC Note: 1. NC” are No Connection pins that are reserved for possible future enhancements. Do not connect these pins to any power, ground, signal traces, or vias. 2. An OVERBAR indicates the signal is asserted when the voltage = ground (active low). Table 3-10 DSP56002 Signal Identification by PGA Pin Number (Continued) Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name MOTOROLA DSP56002/D, Rev. 3 3-27 Packaging Pin-out and Package InformationTable 3-11 DSP56002 PGA Pin Identification by Signal Name Signal Name Pin No. Signal Name Pin No. Signal Name Pin No. A0 K9 D3 L3 DSO L11 A1 L9 D4 L2 EXTAL C8 A2 M9 D5 K3 GNDA N10 A3 L8 D6 K2 GNDA N8 A4 M8 D7 J3 GNDA N6 A5 M7 D8 J2 GNDA N5 A6 L7 D9 H3 GNDA N3 A7 M6 D10 H2 GNDC N13 A8 L6 D11 H1 GNDCK C4 A9 M5 D12 G3 GNDD N1 A10 L5 D13 G2 GNDD L1 A11 K5 D14 G1 GNDD K1 A12 M4 D15 F1 GNDD E1 A13 L4 D16 F2 GNDD D1 A14 K4 D17 F3 GNDD B1 A15 J4 D18 E2 GNDH A12 BG K12 D19 E3 GNDH A13 BN H13 D20 D2 GNDH C13 BR L12 D21 D3 GNDH E13 BS N11 D22 E4 GNDP C6 CKOUT C5 D23 D4 GNDQ A1 CKP B4 DR K11 GNDQ A2 D0 N2 DS L10 GNDQ A5 D1 M3 DSCK N12 GNDQ A7 D2 M2 DSI M11 GNDS J13 3-28 DSP56002/D, Rev. 3 MOTOROLA Packaging Pin-out and Package InformationGNDS L13 PB5 B12 SCK F12 H0 E11 PB6 A11 SCLK E12 H1 D11 PB7 B11 SRD G13 H2 C11 PB8 C9 STD G11 H3 E10 PB9 B9 TIO H11 H4 D10 PB10 A9 TXD D12 H5 B12 PB11 D9 VCCA N9 H6 A11 PB12 B10 VCCA N7 H7 B11 PB13 C10 VCCA N4 HA0 C9 PB14 A10 VCCC M13 HA1 B9 PC0 C12 VCCCK B2 HA2 A9 PC1 D12 VCCD M1 HACK A10 PC2 E12 VCCD J1 HEN B10 PC3 F11 VCCD C1 HR/W D9 PC4 G12 VCCH B13 HREQ C10 PC5 F13 VCCH D13 IRQA C3 PC6 F12 VCCP B5 IRQB C2 PC7 G13 VCCQ A2 MODA C3 PC8 G11 VCCQ A4 MODB C2 PCAP B6 VCCQ A6 MODC D5 PINIT C7 VCCQ A8 NMI D5 PLOCK B7 VCCS K13 OS0 M11 PS M10 WR J11 OS1 N12 RD J10 WT J12 PB0 E11 RESET B3 X/Y K10 PB1 D11 RXD C12 XTAL B8 PB2 C11 SC0 F11 nc H12 PB3 E10 SC1 G12 nc M12 PB4 D10 SC2 F13 Table 3-11 DSP56002 PGA Pin Identification by Signal Name (Continued) Signal Name Pin No. Signal Name Pin No. Signal Name Pin No. MOTOROLA DSP56002/D, Rev. 3 3-29 Packaging Pin-out and Package InformationPower and ground pins have special considerations for noise immunity. See the section Design Considerations. Table 3-12 DSP56002 Power Supply Pins in PGA Package Pin Number Power Supply Circuit Supplied N9 VCCA Address Bus Buffers N7 N4 N10 GNDA N8 N6 N5 N3 M13 VCCC Bus Control BuffersN13 GNDC B2 VCCCK Clock C4 GNDCK M1 VCCD Data Bus Buffers J1 C1 N1 GNDD L1 K1 E1 D1 B1 B13 VCCH Host Interface Buffers D13 A12 GNDH A13 C13 E13 3-30 DSP56002/D, Rev. 3 MOTOROLA Packaging Pin-out and Package InformationA8 VCCQ Internal Logic A6 A4 A2 A1 GNDQ A2 A5 A7 B5 VCCP PLL C6 GNDP K13 VCCS Serial PortJ13 GNDSL13 Figure 3-9 132-pin Ceramic Pin Grid Array (PGA) Package Mechanical Information Table 3-12 DSP56002 Power Supply Pins in PGA Package (Continued) Pin Number Power Supply Circuit Supplied NOTES: 1. 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. 2. CONTROLLING DIMENSION: INCH. DIM MIN MAX INCHES A 1.340 1.380 B 1.340 1.380 C 0.100 0.150 D 0.017 0.022 G 0.100 BSC K 0.170 0.195 -A- -B- C K D 132 PL -T- SAM0.005 B ST 1 2 3 4 5 6 7 8 9 10 11 12 13 A B C D E F G H J K L M N G G CASE 789B-01 ISSUE O MOTOROLA DSP56002/D, Rev. 3 3-31 Packaging Ordering DrawingsORDERING DRAWINGS Complete mechanical information regarding DSP56002 packaging is available by facsimile through Motorola's Mfax™ system. Call the following number to obtain information by facsimile: The Mfax automated system requests the following information: • The receiving facsimile telephone number including area code or country code • The caller’s Personal Identification Number (PIN) Note: For first time callers, the system provides instructions for setting up a PIN, which requires entry of a name and telephone number. • The type of information requested: – Instructions for using the system – A literature order form – Specific part technical information or data sheets – Other information described by the system messages A total of three documents may be ordered per call. The DSP56002 132-pin PQFP package mechanical drawing is referenced as 831A-02. The reference number for the 144-pin TQFP package is 918-03. The reference number for the 132-pin ceramic PGA package is 789B-01. (602) 244-6591 3-32 DSP56002/D, Rev. 3 MOTOROLA SECTION 4 DESIGN CONSIDERATIONS HEAT DISSIPATION An estimation of the chip junction temperature, TJ, in ° C can be obtained from the equation: Equation 1: Where: TA = ambient temperature ˚C R q JA = package junction-to-ambient thermal resistance ˚C/W PD = power dissipation in package Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: Equation 2: Where: R q JA = package junction-to-ambient thermal resistance ˚C/W R q JC = package junction-to-case thermal resistance ˚C/W R q CA = package case-to-ambient thermal resistance ˚C/W R q JC is device-related and cannot be influenced by the user. The user controls the thermal environment to change the case-to-ambient thermal resistance, R q CA. For example, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the Printed Circuit Board, or otherwise change the thermal dissipation capability of the area surrounding the device on a Printed Circuit Board. This model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where the heat flow is split between a path to the case and an alternate path through the Printed Circuit Board, analysis of the device thermal performance may need the additional modeling capability of a system level thermal simulation tool. The thermal performance of plastic packages is more dependent on the temperature of the Printed Circuit Board to which the package is mounted. Again, if the TJ TA PD R q JA·( )+= R q JA R q JC R q CA+= MOTOROLA DSP56002/D, Rev. 3 4-1 Design Considerations Heat Dissipation estimations obtained from R q JA do not satisfactorily answer whether the thermal performance is adequate, a system level model may be appropriate. A complicating factor is the existence of three common ways for determining the junction-to-case thermal resistance in plastic packages: • To minimize temperature variation across the surface, the thermal resistance is measured from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. • To define a value approximately equal to a junction-to-board thermal resistance, the thermal resistance is measured from the junction to where the leads are attached to the case. • If the temperature of the package case (TT) as determined by a thermocouple, the thermal resistance is computed using the value obtained by the equation (TJ – TT)/PD. As noted above, the junction-to-case thermal resistances quoted in this data sheet are determined using the first definition. From a practical standpoint, that value is also suitable for determining the junction temperature from a case thermocouple reading in forced convection environments. In natural convection, using the junction-to-case thermal resistance to estimate junction temperature from a thermocouple reading on the case of the package will estimate a junction temperature slightly hotter than actual temperature. Hence, the new thermal metric, Thermal Characterization Parameter or Y JT, has been defined to be (TJ – TT)/PD. This value gives a better estimate of the junction temperature in natural convection when using the surface temperature of the package. Remember that surface temperature readings of packages are subject to significant errors caused by inadequate attachment of the sensor to the surface and to errors caused by heat loss to the sensor. The recommended technique is to attach a 40-gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy. Note: Table 2-2 Thermal Characteristics on page 2-2 contains the package thermal values for this chip. 4-2 DSP56002/D, Rev. 3 MOTOROLA Design Considerations Electrical Design Considerations ELECTRICAL DESIGN CONSIDERATIONS Use the following list of recommendations to assure correct DSP operation: • Provide a low-impedance path from the board power supply to each VCC pin on the DSP, and from the board ground to each GND pin. • Use at least four 0.1 m F bypass capacitors positioned as close as possible to the four sides of the package to connect the VCC power source to GND. • Ensure that capacitor leads and associated printed circuit traces that connect to the chip VCC and GND pins are less than 0.5 inch per capacitor lead. • Use at least a four-layer Printed Circuit Board (PCB) with two inner layers for VCC and GND. • Because the DSP output signals have fast rise and fall times, PCB trace lengths should be minimal. This recommendation particularly applies to the address and data buses as well as the RD, WR, IRQA, IRQB, NMI, HEN, and HACK pins. • Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the VCC and GND circuits. • All inputs must be terminated (i.e., not allowed to float) using CMOS levels. • Take special care to minimize noise levels on the PLL supply pins (both VCC and GND). CAUTION This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either GND or VCC). MOTOROLA DSP56002/D, Rev. 3 4-3 Design Considerations Power Consumption POWER CONSUMPTION Power dissipation is a key issue in portable DSP applications. The following describes some factors which affect current consumption. Current consumption is described by the formula: Equation 3: where: C = node/pin capacitance V = voltage swing f = frequency of node/pin toggle For example, for an address pin loaded with a 50 pF capacitance and operating at 5.5 V with a 40 MHz clock, toggling at its maximum possible rate (which is 10 MHz), the current consumption is: Equation 4: The maximum internal current value (ICCI-max), reflects the maximum ICC expected when running the code given below. This represents “typical” internal activity, and is included as a point of reference. Some applications may consume more or less current depending on the code used. The typical internal current value (ICCI-typ) reflects what is typically seen when running the given code. The following steps are recommended for applications requiring very low current consumption: 1. Minimize external memory accesses; use internal memory accesses instead. 2. Minimize the number of pins that are switching. 3. Minimize the capacitive load on the pins. 4. Connect the unused inputs to pull-up or pull-down resistors. I C V f··= I 50 10 12–· 5.5· 10· 106· 2.75mA= = 4-4 DSP56002/D, Rev. 3 MOTOROLA Design Considerations Power Consumption Current consumption test code: org p:RESET jmp MAIN org p:MAIN movep #$180000,x:$FFFD move #0,r0 move #0,r4 move #$00FF, m0 move #$00FF, m4 nop rep #256 move r0,x:(r0)+ rep #256 mov r4,y:(r4)+ clr a move l:(r0)+,a rep #30 mac x0,y0,a x:(r0)+,x0 y:(r4)+,y0 move a,p:(r5) jmp TP1 TP1 nop jmp MAIN MOTOROLA DSP56002/D, Rev. 3 4-5 Design Considerations Host Port Considerations HOST PORT CONSIDERATIONS Careful synchronization is required when reading multibit registers that are written by another asynchronous system. This is a common problem when two asynchronous systems are connected. The situation exists in the host interface. The following paragraphs present considerations for proper operation. Host Programming Considerations UNSYNCHRONIZED READING OF RECEIVE BYTE REGISTERS When reading receive byte registers (RXH, RXM, and RXL) the host programmer should use interrupts or poll the RXDF flag that indicates that data is available. This assures that the data in the receive byte registers will be stable. OVERWRITING TRANSMIT BYTE REGISTERS The host programmer should not write to the transmit byte registers (TXH, TXM, and TXL) unless the TXDE bit is set indicating that the transmit byte registers are empty. This guarantees that the transmit byte registers will transfer valid data to the HRX register. SYNCHRONIZATION OF STATUS BITS FROM DSP TO HOST HC, HREQ, DMA, HF3, HF2, TRDY, TXDE, and RXDF status bits are set or cleared from inside the DSP and read by the host processor. The host can read these status bits very quickly without regard to the clock rate used by the DSP, but the possibility exists that the state of the bit could be changing during the read operation. This is generally not a system problem, since the bit will be read correctly in the next pass of any host polling routine. Note: Refer to DSP56002 User’s Manual sections describing the I/O Interface and Host/DMA Interface Programming Model for descriptions of these status bits. OVERWRITING THE HOST VECTOR The Host programmer should change the Host Vector register only when the Host Command bit (HC) is clear. This change guarantees that the DSP interrupt control logic will receive a stable vector. 4-6 DSP56002/D, Rev. 3 MOTOROLA Design Considerations Host Port Considerations CANCELLING A PENDING HOST COMMAND EXCEPTION The host processor may elect to clear the HC bit to cancel the Host Command Exception request at any time before it is recognized by the DSP. Because the host does not know exactly when the exception will be recognized (due to exception processing synchronization and pipeline delays), the DSP may execute the Host Command Exception after the HC bit is cleared. For these reasons, the HV bits must not be changed at the same time the HC bit is cleared. VARIANCE IN THE HI TIMING HI timing may vary during initial startup during the time after reset before the PLL locks. Therefore, before a host attempt to load (i.e., bootstrap) the DSP, the host should first make sure that the HI port programming has been completed. The following steps can be used to ensure that the programming is complete: 1. Set the INIT bit in the ICR 2. Poll the INIT bit until it is cleared. 3. Read the ISR. An alternate method is: 1. Write the TREQ/RREQ together with INIT. 2. Poll INIT, ISR, and the HREQ pin. DSP Programming Considerations SYNCHRONIZATION OF STATUS BITS FROM HOST TO DSP DMA, HF1, HF0, and HCP, HTDE, and HRDF status bits are set or cleared by the host processor side of the interface. These bits are individually synchronized to the DSP clock. Note: Refer to DSP56002 User’s Manual sections describing the I/O Interface and Host/DMA Interface Programming Model for descriptions of these status bits. READING HF0 AND HF1 AS AN ENCODED PAIR A potential problem exists when reading status bits HF0 and HF1 as an encoded pair (i.e., the four combinations 00, 01, 10, and 11 each have significance). A very small probability exists that the DSP will read the status bits synchronized during transition. The solution to this potential problem is to read the HF0 and HF1 bits twice and check for consensus. MOTOROLA DSP56002/D, Rev. 3 4-7 Design Considerations Package Compatibility PACKAGE COMPATIBILITY The PQFP and TQFP packages are designed so that a single Printed Circuit Board (PCB) can accommodate either package. The two package pinouts are similarly sequenced. Proper orientation of each package with the smaller TQFP footprint inside the PQFP footprint allow connection of PCB traces to either package. For example, the D0 pin is near the corner of both the PQFP package (pin 84) and the TQFP package (pin 109), and is adjacent to D1 on both packages. Note: Some “no connect” pins in the TQFP pin sequence are excluded from the PQFP pin sequence. 4-8 DSP56002/D, Rev. 3 MOTOROLA MOTOROLA DSP56002/D, Rev. 3 5-1 SECTION 5 ORDERING INFORMATION DSP56002 ordering information in the table below lists the pertinent information needed to place an order. Consult a Motorola Semiconductor sales office or authorized distributor to determine availability and to order parts. Table 5-1 DSP56002 Ordering Information Part Supply Voltage Package Type Pin Count Frequency (MHz) Order Number DSP56002 5 V Plastic Quad Flat Pack (PQFP) 132 40 DSP56002FC40 66 DSP56002FC66 80 DSP56002FC80 Plastic Thin Quad Flat Pack (TQFP) 144 40 DSP56002PV40 66 DSP56002PV66 80 DSP56002PV80 Ceramic Pin Grid Array 132 40 DSP56002RC40 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. 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