Bài giảng Digital Electronics - Bài 5 - Pham Ngoc Nam

end entity MUX21; The black box interface architecture Behav of MUX21 is begin Y <= A when (S=‘1’) else B; end architecture Behav ; Behavioral description 28 architecture Struct of MUX21 is signal U,V,W : bit; component AND2 is port ( X,Y: in bit; Z: out bit); end component AND2; component OR2 is port ( X,Y: in bit; Z: out bit); end component OR2; component INV is port ( X: in bit; Z: out bit); end component INV; begin Gate1: component INV port map (X=>S,Z=>U); Gate2: component AND2 port map (X=>A,Y=>S,Z=>W); Gate3: component AND2 port map (X=>U,Y=>B,Z=>V); Gate4: component OR2 port map (X=>W,Y=>V,Z=>Y); end architecture Struct ; A First look at VHDL:Example 3 Build a 2-to-1 MUX using both a behav. as well as a structural description A S B Y Structural description A S B Y U V W 29 A First look at VHDL:Example 3 Assume that we want to use the previously declared AND3, OR3 and INV for this structural description of MUX configuration Use3InputGates of MUX21 is for Behav end for; for Struct for Gate1:INV use entity INV(RTL) port map (A=>X,Y=>Z); end for ; for All:AND2 use entity AND3(RTL) port map (A=>X,B=>Y, C=>’1’ ,Y=>Z); end for ; for Gate4:OR2 use entity OR3(RTL) port map (A=>X,B=>Y, C=>’0’ ,Y=>Z); end for ; end for ; end configuration Use3InputGates; Entities A B C Y A Y Components X Y Z X Z 30 A First look at VHDL:Test bench How can we verify the circuit that we made? We have to apply representative stimuli to the circuit and check whether the outputs are correct A VHDL ‘test bench’ can be considered to be the top level of a design It instantiates the Design Under Test (DUT) applies stimuli to it checks whether the stimuli are corrector captures the outputs for visualisation in a waveform viewer 31 A First look at VHDL:Test bench Create a test bench for the behavioral version of the MUX MUX21 A B Y S entity Testbench is end entity Testbench ; Testbench is self-contained: no ports architecture BehavTest of Testbench is Signal In1,In2,Select,Out : bit; begin DUT: entity MUX21(Behav) port map (In1, In2, Select, Out); Stimulus: process is begin In1<=‘0’;In2<=‘1’;Select<=‘0’; wait for 20 ns; Select<=‘1’; wait for 20 ns; In1<=‘1’;In2<=‘0’; wait for 20 ns; ... end process Stimulus; end architecture BehavTest ; 32 A First look at VHDL:Re-use Often, parts of a design can be re-used in another design New products in industry often contain 95% of re-used parts and 5% is newly designed: evolutionary design VHDL encourages this by the concept of ‘Packages’ A ‘Package’ contains definitions of constant values, component declarations, user data types, and sub-programs of VHDL code But first the concept ‘Library’: a library is name of directory into which the binary code resulting from analysis/compilation is stored. Default: WORK 33 A First look at VHDL:Re-use Package interface declaration: package Package_name is -- constants -- user defined types -- component declarations -- sub programs end package Package_name; How to use a package? use Library_name.Package_name.all; U1: entity Package_name.Entity_name(Architecture_name); 34 Language based HW design:a VHDL primer Introduction A first look at VHDL Signals and data types VHDL operators Concurrent versus sequential statements Sequential construction statements Higher performance, less portability:e.g. synthesis issues for Xilinx 35 Signals and Data Types:Predefined signal types package Standard is type Bit is (‘0’,’1’); type Boolean is (False, True); type Character is (--ASCII set); type Integer is range implementation_defined; type Real is range implementation_defined; type Bit_vector is (--array of bits); type String is (--array of characters); type Time is range implementation_defined; end package Standard; Bit, Boolean and Character are enumeration types All standard types are ‘unresolved’ (see later for the meaning of this) 36 Signals and Data Types:Predefined signal types Examples of integer declarations: type Year is range 0 to 99; type Memory_address is range 65535 downto 0; Examples of real declarations: type Probability is range 0.0 to 1.0; type Input_level is range -5.0 to 5.0; A Bit_vector is a collection of bits; a value is specified between double quotes: constant State1: bit_vector(4 downto 0) := “00100”; A String is a collection of characters; a value is specified between double quotes: constant Error_message: string := “Unknown error: ask your poor sysop for help”; Checked by simulator MSB, bit 4 LSB 37 Signals and Data Types:Predefined signal types Time is a physical type: type Time is range implementation_defined units fs ; ps = 1000 fs ; ns = 1000 ps ; us = 1000 ns; ms = 1000 us; sec = 1000 ms; min = 60 sec; hr = 60 min; end units ; Primary unit: resolution limit Secondary units Examples of use: wait for 20 ns; constant Sample_period: time := 2 ms; constant Clock_period: time := 50 ns; 38 Signals and Data Types:User defined physical types The user may define his/her own physical types: type Length is range 0 to 1E9 units um; mm = 1000 um; m = 1000 mm; km = 1000 m; mil = 254 um; inch = 1000 mil; foot = 12 inch; yard = 3 foot; end units ; Primary unit: resolution limit Metric secondary units Imperial secondary units 39 Signals and Data Types:User defined enumeration types The user may define his/her own enumeration types: type FSM_states is (reset, wait, input, calculate, output); Not all synthesis tools support enumerated types When they do support them, the default encoding is often straightforward encoding using the minimum number of bits Often , the default encoding may be over-written by somewhere specifying something like “encoding_style is gray_code” or by explicitly specifying the encoding for each possible value: constant reset: bit_vector := “10000”; constant wait: bit_vector := “01000”; constant input: bit_vector := “00100”; constant calculate: bit_vector := “00010”; constant output: bit_vector := “00001”; 40 Signals and Data Types:Array types The user may define arrays of types: type 1D_array is array (1 to 10) of integer; type 2D_array is array (5 downto 0, 1 to 10) of real; Keep in mind that a vector of bits has NO numerical meaning and that hence arithmetic operations on vectors of bits make no sense: signal Bus,Address : bit_vector (0 to 3); Bus <= Address + 1; -- This makes no sense!!! Solution: via operator overloading (cf. C++): - two functions ‘+’ will exist, one working on integers and one working on vectors of bits - the latter is defined in a vendor specific ‘vector arithmetic package’ that should be use ’d at the beginning of your VHDL 41 Signals and Data Types:Standard logic We have seen that we need more logic levels than just ‘0’ and ‘1’ (e.g. don’t care, unknown after setup violation, ) Therefore the IEEE defined in standard number 1164 9-valued logic signals and operations on them: use always those instead of ‘bit’!! Exists in unresolved form ( std_ulogic ) and resolved form (std_logic) -- again: see later for meaning Exists in single bit and array form: constant A: std_ulogic := ‘U’; -- unitialized constant B: std_logic := ‘U’; constant C: std_ulogic_vector (0 to 15); constant D: std_logic_vector (15 downto 0); 42 Signals and Data Types:Standard logic library IEEE; use IEEE.Std_logic_1164.All; type std_logic is ( ‘U’, -- uninitialized e.g. after power-up ‘X’, -- strongly driven unknown e.g. after setup violation ‘0’, -- strongly driven logic zero ‘1’, -- strongly driven logic one ‘Z’, -- high impedance e.g. not driven at all ‘W’, -- weakly driven unknown ‘L’, -- weakly driven logic zero ‘H’, -- weakly driven logic one ‘-’); -- don’t care 43 Signals and Data Types:Assignment to signals Is the following code valid? signal Z,A,B: std_ulogic ; Z <= A; Z <= B; No, because: - all statements are concurrently valid and are not executed sequentially as in SW languages - when A=‘0’ and B=‘1’, we have a short circuit A B Z A B Z R Resolver circuit 44 Signals and Data Types:Assignment to signals VHDL is a single assignment language for unresolved data types For resolved data types (std_logic & std_logic_vector), the resolver circuit is inferred by the synthesis tool A B Z R Resolver circuit signal Z,A,B: std_logic; Z <= A; Z <= B; 45 Signals and Data Types:Assignment to signals When an array is assigned to another array, both arrays must have same size Assignment is by position, not by index!!! signal Down: std_logic_vector (3 downto 0); signal Up: std_logic_vector (0 to 3); Up <= Down; Which of the two following interpretations is correct? Up(0) Up(1) Up(2) Up(3) Down(3) Down(2) Down(1) Down(0) OR Up(0) Up(1) Up(2) Up(3) Down(0) Down(1) Down(2) Down(3) Correspondence by position! 46 Signals and Data Types:Assignment to signals Assignment to a part of an array is possible Make sure that the direction ( to or downto ) is the same as in the declaration signal Bus: std_logic_vector (7 downto 0); signal A: std_logic_vector (0 to 3); Which of the following VHDL codes is correct? Bus(0 to 3) <= A; Bus <= A; Bus(3 downto 0) <= A; Bus(5 downto 4) <= A(0 to 1); Bus(5 downto 4) <= A(0 to 1); Bus(4 downto 3) <= A(2 to 3); Direction of Bus differs from declaration Array sizes do not match OK! Bus(3) is driven by A(0) OK! Bus(5) is driven by A(0) OK! Bus(4) is driven by A(1) and by A(2): resolved data type use with care!! 47 Signals and Data Types:Assignment to signals ‘Concatenation’: bring wire bundles together to assign them to a bigger array signal Byte_bus: std_logic_vector(7 downto 0); signal Nibble_busA , Nibble_busB : std_logic_vector(3 downto 0); Byte_bus <= Nibble_busA & Nibble_busB ; Byte_bus(7) Byte_bus(6) Byte_bus(5) Byte_bus(4) Byte_bus(3) Byte_bus(2) Byte_bus(1) Byte_bus(0) Nibble_busA(3) Nibble_busA(2) Nibble_busA(1) Nibble_busA(0) Nibble_busB(3) Nibble_busB(2) Nibble_busB(1) Nibble_busB(0) 48 Signals and Data Types:Assignment to signals ‘Aggregation’: alternative method to assign multiple small arrays to a bigger array Not supported by all synthesis tools!! signal X,Y,Z,T: std_logic_vector(3 downto 0); signal A,B,C: std_logic; X <= (A,B,C,C); -- correspondence by position Y A, 1 downto 0 => C, 2 => B); Z A, 2 => B, others => C); T ‘0’); -- initialization irrespective of width of T 49 Signals and Data Types:Generic constants Allows to parameterize behavior Enables re-use of entities in slightly changing environments Makes VHDL much more powerful than schematic entry Generic constants need to have a value at synthesis time! entity General_mux is generic ( width : integer); port ( Input : in std_logic_vector ( width - 1 downto 0); Select : in integer range 0 to width - 1; Output : out std_logic); end entity General_mux ; 50 Generic constants entity General_mux is generic ( width : integer); port ( Input : in std_logic_vector ( width - 1 downto 0); Select : in integer range 0 to width - 1; Output : out std_logic); end entity General_mux ; architecture Behav of General_mux is begin Output <= Input(Select); end architecture Behav ; entity Testbench is end entity Testbench ; architecture Build1 of Testbench is constant Input_size : integer := 8; signal A : std_logic_vector (Input_size-1 downto 0); signal S : integer range 0 to Input_size - 1; signal B : std_logic; begin DUT: entity General_mux(Behav ) generic map ( width => Input_size) port map (Input => A, Select => S, Output => B); ... end architecture Build1; This is not valid VHDL: index is not known at design time! We will replace this by valid code later! 51 Language based HW design:a VHDL primer Introduction A first look at VHDL Signals and data types VHDL operators Concurrent versus sequential statements Sequential construction statements Higher performance, less portability:e.g. synthesis issues for Xilinx 52 Logical Operators List of logical operators: not, and, or, xor, nand, nor Precedence: ‘not’ has highest precedence all others have equal precedence, lower than ‘not’ Logical operators are predefined for following data types: bit, bit_vector, boolean, std_logic, std_logic_vector, std_ulogic, std_ulogic_vector A logical operator may work on an array: arrays should have same size elements are matched by position 53 Logical Operators library IEEE; use IEEE.Std_Logic_1164.All; entity Gate is port ( A,B,C: in std_logic; Z: out std_logic); end entity Gate; architecture Logical of Gate is begin Z <= A and not (B or C); end architecture Logical; 54 Logical Operators library IEEE; use IEEE.Std_Logic_1164.All; entity Gate is generic ( width : integer range 0 to 31); port ( A,B,C: in std_logic_vector( width -1 downto 0); Z: out std_logic_vector( width -1 downto 0)); end entity Gate; architecture Logical of Gate is begin Z <= A and not (B or C); end architecture Logical; 55 Relational Operators List of relational operators: , >, =, /= Relational operators return a boolean Both operands need to be of the same type A relational operator may work on an array: arrays may have different size!! They are left alligned and the number of bits equal to the smallest array are compared; the comparison is done bit by bit, from left to right Remember: vectors of bits do not have a numerical meaning!! However, this comparison works on vectors of bits with the meaning of an unsigned integer when both vectors have equal length 56 Relational Operators library IEEE use IEEE.Std_Logic_1164.All; entity Compare is port ( A: in std_logic_vector(3 downto 0); B: in std_logic_vector(0 to 4); Z: out boolean ); end entity Compare; architecture Relational of Compare is begin Z <= TRUE when A<B else FALSE; end architecture Relational; entity Testbench end entity Testbench ; architecture Build1 of Testbench is signal A: std_logic_vector(3 downto 0) := “1110”; signal B: std_logic_vector(0 to 4) := “10111”; signal Z: boolean ; begin DUT: entity Compare(Relational) port map (A => A, B => B, Z => Z); end architecture Build1; What is the value of Z? TRUE? FALSE? 1110 is compared to 1011 by bit position from left to right; in the 2nd position A(2) > B(1) hence (A<B) is FALSE 57 Arithmetic Operators List of arithmetic operators: +, -, *, /, ** (exponential), abs (absolute value), mod (modulus), rem (remainder) They are defined on types integer and real (except mod and rem ) and not on vectors of bits; use overloading package for the latter (vendor dependent) Both operands have to be of same type; different ranges are allowed A variable of physical type (e.g. time) may be multiplied by an integer or real and will still return a variable of the physical type 58 Arithmetic Operators entity Add is port ( A,B: in integer range 0 to 7; Z: out integer range 0 to 14); end entity Add; architecture Behav of Add is begin Z <= A + B; end architecture Behav ; 59 Language based HW design:a VHDL primer Introduction A first look at VHDL Signals and data types VHDL operators Concurrent versus sequential statements Sequential construction statements Higher performance, less portability:e.g. synthesis issues for Xilinx 60 Concurrent Statements All statements are concurrent and are continuously valid: this mimics the behavior of hardware, where all gates operate concurrently entity Concurrent is port ( A,B,C,D: in std_logic; Y,Z: out std_logic); end entity Concurrent; architecture Struct of Concurrent is begin NAND1: entity NAND2 port map (A,B,Y); NAND2: entity NAND2 port map (C,D,Z); end architecture Struct ; A B C D Y Z Schematic: What is the difference in behavior when NAND1 is specified after NAND2? 61 Concurrent Statements All statements are concurrent and are continuously valid: this mimics the behavior of hardware, where all gates operate concurrently entity Concurrent is port ( A,B,C,D: in std_logic; Y,Z: out std_logic); end entity Concurrent; architecture Struct of Concurrent is begin NAND2: entity NAND2 port map (C,D,Z); NAND1: entity NAND2 port map (A,B,Y); end architecture Struct ; A B C D Y Z Schematic: Behavior is exactly the same!!! 62 Concurrent Statements A B D Z Schematic: T1 Does this schematic specify sequential Behavior? Yes No entity Concurrent is port ( A,B, D: in std_logic; Z: out std_logic); end entity Concurrent; architecture Struct of Concurrent is signal T1: std_logic; begin NAND2: entity NAND2 port map (T1,D,Z); NAND1: entity NAND2 port map (A,B,T1); end architecture Struct ; Both gates continuously update their outputs 63 Simulation This continuously updating of outputs poses problems to the simulator: even if nothing in the circuit changes, the simulator has to compute continuously the ‘new’ outputs of all gates Solution: event-driven simulation a statement is only re-evaluated when one or more of its input signals changes (i.e. when an event occurs at one of its inputs) we say that a statement is sensitive to all its input signals, because an event at any input signals triggers a re-evaluation keep in mind that this mechanism is only for making simulation fast while maintaining the same behavior as in reality, where all gates work continuously!! 64 Simulation How is an event-driven simulator practically implemented? 1. Put all statements with at least one changed input in the ‘process execution queue’ 2. Execute all statements in the process execution queue one by one (or concurrently if the simulator is executed on a parallel computer) without updating the output signals 3. After all statements in the process execution queue are processed, update the output signals 4. Add all statements to the process execution queue that have an event because of the updated output signals 6. Advance system time to the next time where a timed event is planned (e.g. testbench : waitfor 20 ns) 5. Repeat until the process execution queue is empty Delta cycle Delta cycle convergence 65 Simulation entity Flipflop is port ( A,B: in std_logic; Q,Q’: out std_logic); end entity Flipflop ; architecture Struct of FlipFlop is begin NAND2: entity NAND2 port map (Q’,B,Q); NAND1: entity NAND2 port map (A,Q,Q’); end architecture Struct ; Step 1: Put statements with input event in PEQ Process Execution Queue T1 Process Execution Queue T2 A B Q Q’ A B Q Q’ T1 T2 NAND1 NAND1 NAND2 66 Simulation entity Flipflop is port ( A,B: in std_logic; Q,Q’: out std_logic); end entity Flipflop ; architecture Struct of FlipFlop is begin NAND2: entity NAND2 port map (Q’,B,Q); NAND1: entity NAND2 port map (A,Q,Q’); end architecture Struct ; Step 2: Execute statements in PEQ and remember output Process Execution Queue T1 Process Execution Queue T2 A B Q Q’ A B Q Q’ T1 T2 NAND1 NAND1 NAND2 NAND1 Remembered Outputs Q’ <= 1 67 Simulation entity Flipflop is port ( A,B: in std_logic; Q,Q’: out std_logic); end entity Flipflop ; architecture Struct of FlipFlop is begin NAND2: entity NAND2 port map (Q’,B,Q); NAND1: entity NAND2 port map (A,Q,Q’); end architecture Struct ; Step 3: Update outputs Process Execution Queue T1 Process Execution Queue T2 A B Q Q’ A B Q Q’ T1 T2 NAND1 NAND1 NAND2 NAND2 Remembered Outputs Q’ <= 1 68 Simulation entity Flipflop is port ( A,B: in std_logic; Q,Q’: out std_logic); end entity Flipflop ; architecture Struct of FlipFlop is begin NAND2: entity NAND2 port map (Q’,B,Q); NAND1: entity NAND2 port map (A,Q,Q’); end architecture Struct ; Step 4: Add statements with event to PEQ Process Execution Queue T1 Process Execution Queue T2 A B Q Q’ A B Q Q’ T1 T2 NAND1 NAND2 NAND2 End Delta cycle 1 of T1 69 Simulation entity Flipflop is port ( A,B: in std_logic; Q,Q’: out std_logic); end entity Flipflop ; architecture Struct of FlipFlop is begin NAND2: entity NAND2 port map (Q’,B,Q); NAND1: entity NAND2 port map (A,Q,Q’); end architecture Struct ; Step 2: Execute statements in PEQ and remember output Process Execution Queue T1 Process Execution Queue T2 A B Q Q’ A B Q Q’ T1 T2 NAND1 NAND2 NAND2 NAND2 Remembered Outputs Q <= 0 70 Simulation entity Flipflop is port ( A,B: in std_logic; Q,Q’: out std_logic); end entity Flipflop ; architecture Struct of FlipFlop is begin NAND2: entity NAND2 port map (Q’,B,Q); NAND1: entity NAND2 port map (A,Q,Q’); end architecture Struct ; Step 3: Update outputs Process Execution Queue T1 Process Execution Queue T2 A B Q Q’ A B Q Q’ T1 T2 NAND1 NAND2 NAND2 NAND2 Remembered Outputs Q <= 0 71 Simulation entity Flipflop is port ( A,B: in std_logic; Q,Q’: out std_logic); end entity Flipflop ; architecture Struct of FlipFlop is begin NAND2: entity NAND2 port map (Q’,B,Q); NAND1: entity NAND2 port map (A,Q,Q’); end architecture Struct ; Step 4: Add statements with event to PEQ Process Execution Queue T1 Process Execution Queue T2 A B Q Q’ A B Q Q’ T1 T2 NAND1 NAND2 NAND1 End Delta cycle 2 of T1 72 Simulation entity Flipflop is port ( A,B: in std_logic; Q,Q’: out std_logic); end entity Flipflop ; architecture Struct of FlipFlop is begin NAND2: entity NAND2 port map (Q’,B,Q); NAND1: entity NAND2 port map (A,Q,Q’); end architecture Struct ; Step 2: Execute statements in PEQ and remember output Process Execution Queue T1 Process Execution Queue T2 A B Q Q’ A B Q Q’ T1 T2 NAND1 NAND2 NAND1 NAND1 Remembered Outputs Q’ <= 1 73 Simulation entity Flipflop is port ( A,B: in std_logic; Q,Q’: out std_logic); end entity Flipflop ; architecture Struct of FlipFlop is begin NAND2: entity NAND2 port map (Q’,B,Q); NAND1: entity NAND2 port map (A,Q,Q’); end architecture Struct ; Step 3: Update outputs Process Execution Queue T1 Process Execution Queue T2 A B Q Q’ A B Q Q’ T1 T2 NAND1 NAND2 NAND1 NAND1 Remembered Outputs Q’ <= 1 Output does not change 74 Simulation entity Flipflop is port ( A,B: in std_logic; Q,Q’: out std_logic); end entity Flipflop ; architecture Struct of FlipFlop is begin NAND2: entity NAND2 port map (Q’,B,Q); NAND1: entity NAND2 port map (A,Q,Q’); end architecture Struct ; Step 4: Add statements with event to PEQ Process Execution Queue T1 Process Execution Queue T2 A B Q Q’ A B Q Q’ T1 T2 NAND1 NAND2 End Delta cycle 3 of T1: convergence 75 Simulation entity Flipflop is port ( A,B: in std_logic; Q,Q’: out std_logic); end entity Flipflop ; architecture Struct of FlipFlop is begin NAND2: entity NAND2 port map (Q’,B,Q); NAND1: entity NAND2 port map (A,Q,Q’); end architecture Struct ; Step 6: Advance system time Process Execution Queue T1 Process Execution Queue T2 A B Q Q’ A B Q Q’ T1 T2 NAND1 NAND2 76 Simulation entity Flipflop is port ( A,B: in std_logic; Q,Q’: out std_logic); end entity Flipflop ; architecture Struct of FlipFlop is begin NAND2: entity NAND2 port map (Q’,B,Q); NAND1: entity NAND2 port map (A,Q,Q’); end architecture Struct ; Step 2: Execute statements in PEQ and remember output Process Execution Queue T1 Process Execution Queue T2 A B Q Q’ A B Q Q’ T1 T2 NAND1 NAND2 NAND1 Remembered Outputs Q’ <= 1 NAND2 NAND2 Q <= 1 NAND2 computed using this Q’, not the remembered 77 Simulation entity Flipflop is port ( A,B: in std_logic; Q,Q’: out std_logic); end entity Flipflop ; architecture Struct of FlipFlop is begin NAND2: entity NAND2 port map (Q’,B,Q); NAND1: entity NAND2 port map (A,Q,Q’); end architecture Struct ; Step 3: Update outputs Process Execution Queue T1 Process Execution Queue T2 A B Q Q’ A B Q Q’ T1 T2 NAND1 NAND2 NAND1 Remembered Outputs Q’ <= 1 NAND2 NAND2 Q <= 1 78 Simulation entity Flipflop is port ( A,B: in std_logic; Q,Q’: out std_logic); end entity Flipflop ; architecture Struct of FlipFlop is begin NAND2: entity NAND2 port map (Q’,B,Q); NAND1: entity NAND2 port map (A,Q,Q’); end architecture Struct ; Step 4: Add statements with event to PEQ Process Execution Queue T1 Process Execution Queue T2 A B Q Q’ A B Q Q’ T1 T2 NAND1 End Delta cycle 1 of T2 79 Simulation entity Flipflop is port ( A,B: in std_logic; Q,Q’: out std_logic); end entity Flipflop ; architecture Struct of FlipFlop is begin NAND2: entity NAND2 port map (Q’,B,Q); NAND1: entity NAND2 port map (A,Q,Q’); end architecture Struct ; Step 2: Execute statements in PEQ and remember output Process Execution Queue T1 Process Execution Queue T2 A B Q Q’ A B Q Q’ T1 T2 NAND1 NAND1 Remembered Outputs Q’ <= 0 80 Simulation entity Flipflop is port ( A,B: in std_logic; Q,Q’: out std_logic); end entity Flipflop ; architecture Struct of FlipFlop is begin NAND2: entity NAND2 port map (Q’,B,Q); NAND1: entity NAND2 port map (A,Q,Q’); end architecture Struct ; Step 3: Update outputs Process Execution Queue T1 Process Execution Queue T2 A B Q Q’ A B Q Q’ T1 T2 NAND1 NAND1 Remembered Outputs Q’ <= 0 81 Simulation entity Flipflop is port ( A,B: in std_logic; Q,Q’: out std_logic); end entity Flipflop ; architecture Struct of FlipFlop is begin NAND2: entity NAND2 port map (Q’,B,Q); NAND1: entity NAND2 port map (A,Q,Q’); end architecture Struct ; Step 4: Add statements with event to PEQ Process Execution Queue T1 Process Execution Queue T2 A B Q Q’ A B Q Q’ T1 T2 NAND2 End Delta cycle 2 of T2 82 Simulation entity Flipflop is port ( A,B: in std_logic; Q,Q’: out std_logic); end entity Flipflop ; architecture Struct of FlipFlop is begin NAND2: entity NAND2 port map (Q’,B,Q); NAND1: entity NAND2 port map (A,Q,Q’); end architecture Struct ; Step 2: Execute statements in PEQ and remember output Process Execution Queue T1 Process Execution Queue T2 A B Q Q’ A B Q Q’ T1 T2 NAND2 NAND2 Remembered Outputs Q <= 1 83 Simulation entity Flipflop is port ( A,B: in std_logic; Q,Q’: out std_logic); end entity Flipflop ; architecture Struct of FlipFlop is begin NAND2: entity NAND2 port map (Q’,B,Q); NAND1: entity NAND2 port map (A,Q,Q’); end architecture Struct ; Step 3: Update outputs Process Execution Queue T1 Process Execution Queue T2 A B Q Q’ A B Q Q’ T1 T2 NAND2 NAND2 Remembered Outputs Q <= 1 Output does not change 84 Simulation entity Flipflop is port ( A,B: in std_logic; Q,Q’: out std_logic); end entity Flipflop ; architecture Struct of FlipFlop is begin NAND2: entity NAND2 port map (Q’,B,Q); NAND1: entity NAND2 port map (A,Q,Q’); end architecture Struct ; Step 4: Add statements with event to PEQ Process Execution Queue T1 Process Execution Queue T2 A B Q Q’ A B Q Q’ T1 T2 End Delta cycle 3 of T2: convergence 85 Simulation entity Flipflop is port ( A,B: in std_logic; Q,Q’: out std_logic); end entity Flipflop ; architecture Struct of FlipFlop is begin NAND2: entity NAND2 port map (Q’,B,Q); NAND1: entity NAND2 port map (A,Q,Q’); end architecture Struct ; Step 6: Advance system time Process Execution Queue T1 Process Execution Queue T2 A B Q Q’ A B Q Q’ T1 T2 86 Process Sometimes, the combinatorial equation in a single statement becomes very complicated: entity Complex is port ( A,B,C,D,E,F,G,H,I,J: in std_logic; Y,Z: out std_logic); end entity Complex; architecture Struct of Complex is begin Y <= ((A nand B) nand (C nand D)) when (S = ‘1’) else ((E nand F) nand (G nand H)); Z <= I nand J; end architecture Struct ; A B C D E F G H S Y I J Z 87 Process Therefore a process has been defined: a process acts as a single statement that is executed concurrently with all other statements inside a process, commands are executed sequentially in the order they are listed. This makes it easy to break down a very complicated statement into a list of smaller commands to pass data from one command to the other, we may declare temporary variables ; they do not have necessarily a physical realization a statement, and hence also a process, is sensitive to all its input signals; to facilitate finding out what the input signals of a process are, since they can occur in any command, we have to explicitly add them to a sensitivity list . A process is recalculated when a signal in the sensitivity list has an event. Unfortunately, in VHDL terminology they are also called ‘Statements’ 88 Process Syntax of process: Process_name: process (sensitivity_list) is -- variable declarations; begin -- sequential commands end process Process_name; Syntax of variable declaration: variable Variable_name: type; Syntax of variable assignment: Variable_name := expression; When assigning to variable  := When assigning to signal  <= 89 Process Rewrite the example using a process: entity Complex is port ( A,B,C,D,E,F,G,H,I,J: in std_logic; Y,Z: out std_logic); end entity Complex; architecture Struct of Complex is begin Y_process: process (A,B,C,D,E,F,G,H,S) is variable T1,T2: std_logic; begin if (S=‘1’) then T1 := A nand B; T2 := C nand D; else T1 := E nand F; T2 := G nand H; end if ; Y <= T1 nand T2; end process Y_process; Z <= I nand J; end architecture Struct ; A B C D E F G H S Y I J Z T1 and T2 have no physical meaning since each refers to 2 different physical wires T1 T2 Sensitivity list 90 Process Processes and delta cycle convergence. What is the behavior of following process: Example: process (A,B,M) is begin Y <= A; M <= B; Z <= M; end process Example; 1. Assume event at B with new value B’ 2. Process Example is executed once sequentially. Following outputs are remembered: Y’ <= A; M’ <= B’; Z’ <= M; Old M!!! M gets only new value at end of process 3. Process Example suspends (i.e. is executed once completely). Y, M and Z get their new values Y’, M’, Z’. 4. Since M is in the sensitivity list, the Example process is placed again in the Process Execution Queue. 5. Process Example is executed: Y” <= A; M” <= B’; Z” <= M’; 6. Outputs Y, M and Z get their new values Y”, M”, Z”. 7. No signals of the sensitivity list changed => delta cycle convergence 91 Process Processes and delta cycle convergence. What is the behavior of following process: Example: process (A,B,C,D) is begin Z <= A + B; Z <= C + D; end process Example; 1. Assume event at B with new value B’ 2. The commands of Process Example are executed sequentially. First following output is remembered: Z’ <= A + B’; 3. Next, the second command is executed and following output is remembered: Z’ <= C + D. This overwrites the previously remembered Z’ 4. Process Example suspends and hence signal Z is updated with its new value C + D When the same two statements would have occurred outside a process, both would drive signal Z and a resolver would be necessary 92 Language based HW design:a VHDL primer Introduction A first look at VHDL Signals and data types VHDL operators Concurrent versus sequential statements Sequential construction statements Higher performance, less portability:e.g. synthesis issues for Xilinx 93 Sequential construction statements Sequential construction statements are only allowed within a process!!! There are 3 sequential construction statements: IF, CASE, FOR IF statement: if condition then -- sequential statements else -- sequential statements end if ; multiple IF statements: if condition1 then -- sequential statements elseif condition2 then -- sequential statements elseif condition3 then -- sequential statements else -- sequential statements end if ; The first condition which turns out to be TRUE determines which sequential statements are executed: built-in priority 94 Sequential construction statements case Expression is when Value_1 => -- sequential statements when Value_2 => -- sequential statements -- etc. end case ; Example: process (A,B,C,X) is begin case X is when 0 to 4 => Z <= B; when 5 => Z <= C; when 7 | 9 => Z <= A; when others => Z <= ‘0’; end process Example; Requirements: 1. All possible values should be specified 2. The values should be constant and known at design time 3. The values should have the same type as the expression 95 Sequential construction statements for I in 0 to 3 loop -- sequential statements end loop ; 1. The loop variable must not be declared Remarks: 2. The synthesis tool will unfold the loop and create logic for each iteration of the loop. Then, it will start minimizing the complete circuit 96 Sequential construction statements entity General_mux is generic ( width : integer); port ( Input : in std_logic_vector ( width - 1 downto 0); Select : in integer range 0 to width - 1; Output : out std_logic); end entity General_mux ; architecture Behav of General_mux is begin Output <= Input(Select); end architecture Behav ; We indicated that this is not valid VHDL: index is not known at design time! We will replace this now by valid code using the loop construct. 97 Sequential construction statements entity General_mux is generic ( width : integer); port ( Input : in std_logic_vector ( width - 1 downto 0); Select : in integer range 0 to width - 1; Output : out std_logic); end entity General_mux ; architecture Behav of General_mux is begin Selector: process (Input, Select) is begin for I in 0 to width -1 loop if Select=I then Output <= Input(I); end if ; end loop ; end process Selector; end architecture Behav ; 98 Variables A variable can only be used within a process A variable is updated immediately; a signal is stored in the signal update queue till the process suspends Variables may be assigned to signals and vice versa Variables are used as intermediate values to facilitate the specification of the process; when the value of a variable needs to be accessible outside the process, it should be assigned to a signal 99 Variables With which hardware schematic does following code correspond? entity Parity is generic ( width : integer); port (A: in std_logic_vector (0 to width -1); Odd: out std_logic); end entity Parity; architecture Struct of Parity is begin Parity: process (A) is variable Temp: std_logic; begin Temp := ‘0’; for I in A’low to A’high loop Temp := Temp xor A(I); end loop ; Odd <= Temp; end process Parity; end architecture Struct ; 0 A(0) A(1) A(2) Temp Temp Odd This is the HW structure as it is given to the synthesis tool. The synthesis tool will optimize away the xor with constant ‘0’ input and will transform it to a binary tree of less depth 100 Rising clock edge With which function does following code correspond? entity What is port ( D,Clk : in std_logic; Q: out std_logic); end entity What; architecture RTL of What is begin process (D, Clk ) is begin if ( Clk =‘1’) then Q <= D; end if ; end process ; end architecture RTL; With a latch, not with a D-flip-flop!! When a Clk -event occurs and Clk is low, nothing happens When a Clk -event occurs and Clk is high, the D input is copied to the Q output When a D-event occurs and Clk is high, the D input is copied to the Q output => hence a latch: when Clk is high, Q follows D Since there is no ELSE part the previous Q value has to be remembered for the case where Clk =‘0’. The synthesis tool will hence infer a latch instead of just combinatorial logic!!! Beware of unintended latches when ELSE parts are omitted 101 Rising clock edge How do we describe a rising clock edge? Method 1: WAIT UNTIL entity DFlipFlop is port ( D,Clk : in std_logic; Q: out std_logic); end entity DFlipFlop ; architecture RTL of DFlipFlop is begin process is begin wait until Clk’event and Clk =‘1’; Q <= D; end process ; end architecture RTL; This is not synthesisable 102 Rising clock edge How do we describe a rising clock edge? Method 2: Sensitivity list entity DFlipFlop is port ( D,Clk : in std_logic; Q: out std_logic); end entity DFlipFlop ; architecture RTL of DFlipFlop is begin process ( D,Clk ) is begin if ( Clk’event and Clk =‘1’) then Q <= D; end if ; end process ; end architecture RTL; Preferred method! 103 Rising clock edge How do we describe combinatorial circuits with registered outputs? Method 1: WAIT UNTIL entity RegisteredCircuit is port ( A,B,C,D,Clk : in std_logic; Z: out std_logic); end entity RegisteredCircuit ; architecture RTL of RegisteredCircuit is begin process is begin wait until Clk’event and Clk =‘1’; -- combinatorial circuit Z <= (A and B) or (C and D); end process ; end architecture RTL; A B C D Z ‘Wait until’ has to be first line of process, followed by the description of the combinatorial circuit 104 Rising clock edge How do we describe combinatorial circuits with registered outputs? Method 2: Sensitivity list entity RegisteredCircuit is port ( A,B,C,D,Clk : in std_logic; Z: out std_logic); end entity RegisteredCircuit ; architecture RTL of RegisteredCircuit is begin process ( A,B,C,D,Clk ) is begin if ( Clk’event and Clk =‘1’) then -- combinatorial circuit Z <= (A and B) or (C and D); end if ; end process ; end architecture RTL; A B C D Z ‘if Clk’event ’ has to be first line of process, with the description of the combinatorial circuit in the THEN part and with no ELSE part 105 Rising clock edge The amount of logic we describe in the combinatorial part, determines the combinatorial delay It hence determines the maximum clock frequency with which we can clock the flip-flop Re-timing requires re-writing the VHDL code 106 Rising clock edge How do we describe flip-flops with asynchronous reset? entity DFlipFlop is port ( D,Clk , Reset: in std_logic; Q: out std_logic); end entity DFlipFlop ; architecture RTL of DFlipFlop is begin process (D, Clk , Reset) is begin if (Reset = ‘1’) then Q <= ‘0’; elseif ( Clk’event and Clk =‘1’) then Q <= D; end if ; end process ; end architecture RTL; 107 Rising clock edge How do we describe flip-flops with synchronous reset? entity DFlipFlop is port ( D,Clk , Reset: in std_logic; Q: out std_logic); end entity DFlipFlop ; architecture RTL of DFlipFlop is begin process (D, Clk , Reset) is begin if ( Clk’event and Clk =‘1’) then if (Reset=‘1’) then Q <= 0; else Q <= D; end if ; end if ; end process ; end architecture RTL; 108 Finite State Machine Wait 00 Up1 01 Up2 10 Up3 11 Down3 11 Down2 10 Down1 01 Start=0 Start=1 Up=0 Start=1 Up=1 Up Start Next state logic Out put logic State Reg Reset Output NextState CurrentState 109 Finite State Machine Wait 00 Up1 01 Up2 10 Up3 11 Down3 11 Down2 10 Down1 01 Start=0 Start=1 Up=0 Start=1 Up=1 entity FSM is port ( Start, Up, Reset, Clk : in std_logic; Output: out std_logic_vector(0 to 1)); end entity FSM; architecture Behav of FSM is type FSM_States = (Wait,Up1,Up2, Up3,Down1,Down2,Down3); signal CurrentState , NextState : FSM_States; begin OutputLogic : process (CurrentState ) is end process OutputLogic ; NextStateLogic : process (CurrentState,Start,Up ) is end process NextStateLogic ; StateRegister : process (NextState,Clk,Reset ) is end process StateRegister ; end architecture Behav ; 110 Finite State Machine Wait 00 Up1 01 Up2 10 Up3 11 Down3 11 Down2 10 Down1 01 Start=0 Start=1 Up=0 Start=1 Up=1 OutputLogic : process (CurrentState ) is begin case CurrentState is when Wait => Output <= “00”; when Up1|Down1 => Output <= “01”; when Up2|Down2 => Output <= “10”; when Up3|Down3 => Output <= “11”; end case ; end process OutputLogic ; 111 Finite State Machine Wait 00 Up1 01 Up2 10 Up3 11 Down3 11 Down2 10 Down1 01 Start=0 Start=1 Up=0 Start=1 Up=1 NextStateLogic : process (CurrentState,Start,Up ) is begin case CurrentState is when Wait => if (Start=‘0’) then NextState <= Wait; elseif (Up=‘1’) then NextState <= Up1; else NextState <= Down3; end if ; when Up1 => NextState <= Up2; when Up2 => NextState <= Up3; when Up3|Down1 => NextState <= Wait; when Down3 => NextState <= Down2; when Down2 => NextState <= Down1; end case ; end process NextStateLogic ; 112 Finite State Machine Wait 00 Up1 01 Up2 10 Up3 11 Down3 11 Down2 10 Down1 01 Start=0 Start=1 Up=0 Start=1 Up=1 StateRegister : process (NextState,Clk,Reset ) is begin if Reset=‘1’ then CurrentState <= Wait; elseif ( Clk’event and Clk =‘1’) then CurrentState <= NextState ; end if ; end process StateRegister ; 113 Language based HW design:a VHDL primer Introduction A first look at VHDL Signals and data types VHDL operators Concurrent versus sequential statements Sequential construction statements Higher performance, less portability:e.g. synthesis issues for Xilinx 114 Resource sharing What is the circuit corresponding to: if Sel = ‘1’ then Z <= A + B; else Z <= A + C; end if ; + + MUX A B C A Sel Z This is kind of stupid, since both additions are mutually exclusive: it is hence not necessary to implement 2 adders. Some synthesis tools are capable to recognize this (often only within the scope of a process) and transform this into the shared use of one adder for both additions. Xilinx Foundation Series performs this optimization within a hierarchical level. + MUX B C A Z Sel 115 Resource sharing If the synthesis tool does not do this optimization automatically, you should re-write your code: + MUX B C A Z Sel if Sel = ‘1’ then X := B; else X := C; end if ; Z <= A + X; The VHDL coding style together with the capabilities of the synthesis tool determine the circuit that is eventually synthesized. 116 Using LogiBLOX in VHDL LogiBLOX modules lead to highly efficient FPGA implementations The LogiBLOX module generator creates, apart from the FPGA implementation, also a behavioral level VHDL module for simulation! How to use LogiBLOX modules in your VHDL code: use the package containing the LogiBLOX modules: library My_Library; use My_Library.My_Package.all; instantiate the entity Using LogiBLOX makes your VHDL implementation more efficient on Xilinx FPGA but less portable to other devices!! 117 Encoding of State Machines The default encoding in Foundation Express is one-hot since this matches well with the structure of a CLB (little bit of combinatorial logic in front of a D-flip-flop) The encoding can be specified in the VHDL code: type State_Type is (S1, S2, S3, S4); attribute ENUM_ENCODING: string ; attribute ENUM_ENCODING of State_Type: type is “11 10 01 00”; 118 Safe state machines Assume a state machine of three states, encoded with 2 bits What would happen when the state machine enters the 4th state, due to some error (noise, power-up, )? Will it be able to recover? Make provisions for this situation in your VHDL code: NextStateLogic : process (CurrentState ) is begin case CurrentState is when Idle => NextState <= S1; when S1 => NextState <= S2; when S2 => NextState <= Idle; when others => NextState <= Idle; end case ; end process NextStateLogic ; 119 Family specific issues Not all families provide per flip-flop both asynchronous set as well as reset. Check what your family provides before you write VHDL process ( Clk , Rst , Set) is begin if Rst = ‘1’ then Q <= ‘0’; elseif Set = ‘1’ then Q <= ‘1’; elseif Clk’event and Clk = ‘1’ then -- actions end if ; end process ; Can only be implemented efficiently when the family has both an asynchronous set as well as reset 120 Family specific issues Always use LogiBLOX for RAM, because RAM would otherwise be created out of separate flip-flops 121 I/O buffer types Put all the core logic in one entity In a higher hierarchical level, instantiate the I/O buffers as well as the core logic The hierarchy hence becomes Top level: test bench instantiating DUT DUT: Instantiation of core logic and I/O buffers Core logic: real design 122 I/O buffer types How to force a 3-state output buffer: if (Enable = ‘1’) then Out_pad <= Bus_out; else Out_pad <= ‘Z’; end if ; How to force a bidirectional buffer: Bus_in <= Bidi_pad ; process (Enable, Bus_out) is begin if (Enable = ‘1’) then Bidi_pad <= Bus_out; else Bidi_pad <= ‘Z’; end if ; end process ; Enable Bus_out Out_pad Enable Bus_out Bidi_pad Bus_in 123 I/O buffer types How to force a bidirectional buffer with registered output: Bus_in <= Bidi_pad ; process (Enable,Q) is begin if (Enable = ‘1’) then Bidi_pad <= Q; else Bidi_pad <= ‘Z’; end if ; end process ; process ( Clk , Bus_out) is begin if Clk’event and Clk = ‘1’ then Q <= D; end if ; end process ; Enable Bus_out Bidi_pad Bus_in Q D Clk 124 I/O buffer types How to force a pull-up resistor at an input: entity Pullup_in is port ( In_pad: in std_logic; Core_in: out std_logic); end entity Pullup_in ; architecture RTL of Pullup_in is component PULLUP port (O: out std_logic); end component PULLUP; component IBUF port (I: in std_logic; O: out std_logic); end component IBUF; signal Dummy: std_logic; begin Dummy <= In_pad; PU: component PULLUP port map (Dummy); Buf : component IBUF port map (Dummy,Core_in); end architecture RTL; Core_in In_pad V cc 125 Using the Global Set Reset block entity OneHot is port ( Rst , Clk : in std_logic; Q: out std_logic_vector (0 to 3)); end entity OneHot ; architecture Behav of OneHot is component STARTUP port (GSR: out std_logic); end component STARTUP; begin U1: component STARTUP port map ( Rst => GSR); if Rst = ‘1’ then Q <= “0001”; elseif Clk’event and Clk = ‘1’ then Q <= Q(1 to 3) & Q(0); endif ; end architecture RTL; 126 Clock Networks Foundation Express synthesizes automatically clock buffers Check whether you do not need more clock buffers than are available in the target family 127