Bài giảng Digital electronics - VLSI combinational circuit design - Lê Dũng

9/25/13 1 VLSI Combinational Circuit Design Dr.  Le  Dung   Hanoi University of Science and Technology Dr. Le Dung Hanoi University of Science and Technology A  large  digital  logic  circuit   can  be  implemented  by         SSI, MSI and LSI “off-the-shelf” parts VLSI Application-specific integrated circuit (ASIC) Single  IC  Mul:ple  ICs   9/25/13 2 Dr. Le Dung Hanoi University of Science and Technology An example of the “off-the-shelf” parts design Dr. Le Dung Hanoi University of Science and Technology Designing with “off-the-shelf” parts •   The  “off-­‐the-­‐shelf”  parts  =  Commercial  SSI,  MSI  and  LSI   modular  logic  integrated  circuits  (74xxx,  4xxx    )   •   Quickly  assembling  a  circuit  board     •   The  number  of  parts  and  the  cost  per  gate  can  become   unacceptably  large   9/25/13 3 Dr. Le Dung Hanoi University of Science and Technology VLSI ASIC design •   Using  single  VLSI  IC      +  Reduce  PCB  space  and  power  requirements      +  Reduce  total  cost   •   Using  hardware  descrip:on  language  and   CAD  tools  for  designing     •     Designing  approaches  :   +  Full-­‐custom  design   +  Semi-­‐custom  design   Dr. Le Dung Hanoi University of Science and Technology Full-custom design (1) •     Gate  by  gate  designing  with  the  physical  layout  of  each   individual  transistor  and  the  interconnec:ons  between  them.   Each  transistor  and  each  connec:on  is  designed  individually  as   a  set  of  rectangles   9/25/13 4 Dr. Le Dung Hanoi University of Science and Technology Full-custom design (2) +    Both  the  circuit  performance  and  the  silicon  area  can   be  op:mized  (using  ECAD  tools)   -­‐  Extremely  labor-­‐intensive  to  implement   -­‐  High  cost  of  mask  sets   -­‐  Increasing  manufacturing  and  design  :me        Time-­‐to-­‐market  compe::on   Dr. Le Dung Hanoi University of Science and Technology Semi-custom design •   Semi-­‐custom  device      +  has  predesigned  parts       •   Semi-­‐custom  design  approaches      Standard  cell  based  design      Gate  array  based  design      Programmable  devices  based  design       9/25/13 5 Dr. Le Dung Hanoi University of Science and Technology Standard cell based design (1) •  Library  of  standard  cells   +  Each  cell  is  a  gate       +  Same  height,  variable  width,  interleaved  by  rou:ng  channels   +  All  inputs  at  the  top,  all  outputs  at  the  bo]om   •  A  designer  selects  cells  from  a  design  libarary,  specifying   where  they  should  be  placed  on  the  IC  and  then   dicta:ng  how  they  should  be  interconnected.   •  Faster  design  of  more  complex  building  blocks   •  Silicon  foundries  design  and  sell  such  op:mized  libraries   for  their  processing  technology   Dr. Le Dung Hanoi University of Science and Technology Basic process standard cell based design Technology   mapping   9/25/13 6 Dr. Le Dung Hanoi University of Science and Technology Hardware  Descrip:on  Language Synthesis Translate HDL descriptions into logic gate networks in a particular library Dr. Le Dung Hanoi University of Science and Technology Logic  Synthesis  Phases •  Logic optimization transforms current gate-level network into an equivalent gate-level network more suitable for technology mapping. •  Technology mapping transforms the gate-level network into a netlist of gates (from library) which minimizes total cost. 9/25/13 7 Library  of  standard  cell     INVERTER    2                1   NAND2    3                1.4     NAND3    4            1.8   NAND4    5            2.2   AOI21      4            1.8   CELLS                COST        DELAY      SYMBOL                                    PATTERN     Dr. Le Dung Hanoi University of Science and Technology CMOS AND-OR-Invert Gate   An  example  of  standard  cell  technology  mapping  (1)   Dr. Le Dung Hanoi University of Science and Technology 9/25/13 8 An  example  of  standard  cell  technology  mapping  (2)   Synthesis   Dr. Le Dung Hanoi University of Science and Technology Netlist of gates (from library) which minimizes total cost. Phases  of  synthesis  (1/3)   1.   Independent  transformaNons  (opNmizaNon):   Dr. Le Dung Hanoi University of Science and Technology 9/25/13 9 Phases  of  synthesis  (1/3)   Dr. Le Dung Hanoi University of Science and Technology 1.   Independent  transformaNons  (opNmizaNon):   Phases  of  synthesis  (1/3)   Dr. Le Dung Hanoi University of Science and Technology 1.   Independent  transformaNons  (opNmizaNon):   9/25/13 10 Phases  of  synthesis  (1/3)   Dr. Le Dung Hanoi University of Science and Technology 1.   Independent  transformaNons  (opNmizaNon):   Phases  of  synthesis  (1/3)   Dr. Le Dung Hanoi University of Science and Technology 1.   Independent  transformaNons  (opNmizaNon):   9/25/13 11 Phases  of  synthesis  (1/3)   d   a   c   b   e   f   g   h   Dr. Le Dung Hanoi University of Science and Technology 1.   Independent  transformaNons  (opNmizaNon):   Original netlist Phases  of  synthesis  (2/3)   •  DecomposiNon  using  base  funcNons:   –  Decompose  to  a  network  NAND2/NOT   d   a   c   b   e   f  g   h   Dr. Le Dung Hanoi University of Science and Technology Original netlist 9/25/13 12 Phases  of  synthesis  (2/3)   d   a   c   b   e   f  g   h   •  DecomposiNon  using  base  funcNons:   –  Decompose  to  a  network  NAND2/NOT   Dr. Le Dung Hanoi University of Science and Technology Phases  of  synthesis  (2/3)   d   a   c   b   e   f  g   h   •  DecomposiNon  using  base  funcNons:   –  Decompose  to  a  network  NAND2/NOT   Dr. Le Dung Hanoi University of Science and Technology 9/25/13 13 Phases  of  synthesis  (2/3)   d   a   c   b   e   f  g   h   •  DecomposiNon  using  base  funcNons:   –  Decompose  to  a  network  NAND2/NOT   Dr. Le Dung Hanoi University of Science and Technology Phases  of  synthesis  (2/3)   d   a   c   b   e   f  g   h   •  DecomposiNon  using  base  funcNons:   –  Decompose  to  a  network  NAND2/NOT   Dr. Le Dung Hanoi University of Science and Technology 9/25/13 14 Phases  of  synthesis  (2/3)   d   a   c   b   e   f  g   h   •  DecomposiNon  using  base  funcNons:   –  Decompose  to  a  network  NAND2/NOT   Dr. Le Dung Hanoi University of Science and Technology Phases  of  synthesis  (2/3)   d   a   c   b   e   f  g   h   •  DecomposiNon  using  base  funcNons:   –  Decompose  to  a  network  NAND2/NOT   Dr. Le Dung Hanoi University of Science and Technology 9/25/13 15 Phases  of  synthesis  (2/3)   d   a   c   b   e   f  g   h   •  DecomposiNon  using  base  funcNons:   –  Decompose  to  a  network  NAND2/NOT   Dr. Le Dung Hanoi University of Science and Technology Phases  of  synthesis  (2/3)   d   a   c   b   e   f  g   h   •  DecomposiNon  using  base  funcNons:   –  Decompose  to  a  network  NAND2/NOT   Dr. Le Dung Hanoi University of Science and Technology 9/25/13 16 Phases  of  synthesis  (2/3)   d   a   c   b   e   f  g   h   •  DecomposiNon  using  base  funcNons:   –  Decompose  to  a  network  NAND2/NOT   Dr. Le Dung Hanoi University of Science and Technology Phases  of  synthesis  (2/3)   d   a   c   b   e   f  g   h   •  DecomposiNon  using  base  funcNons:   –  Decompose  to  a  network  NAND2/NOT   Dr. Le Dung Hanoi University of Science and Technology 9/25/13 17 Phases  of  synthesis  (2/3)   d   a   c   b   e   f  g   h   •  DecomposiNon  using  base  funcNons:   –  Decompose  to  a  network  NAND2/NOT   Dr. Le Dung Hanoi University of Science and Technology Phases  of  synthesis  (2/3)   d   a   c   b   e   f  g   h   •  DecomposiNon  using  base  funcNons:   –  Decompose  to  a  network  NAND2/NOT   Dr. Le Dung Hanoi University of Science and Technology Subject Graph 9/25/13 18 What  is  technology  mapping  ?     •  Technology  mapping  is  the  problem  of  opNmising  a   network  for  area  or  delay,  using  only  library  cells.   Mapping   library   rule   Dr. Le Dung Hanoi University of Science and Technology Netlist of gates (from library) which minimizes total cost. Original netlist Phases  of  synthesis  (3/3)   d   a   c   b   e   f  g   h   •  Technology  mapping:   Greedy  algorithm    Greedy  search   Dr. Le Dung Hanoi University of Science and Technology Subject Graph 9/25/13 19 Phases  of  synthesis  (3/3)   d   a   c   b   e   f  g   h   •  Technology  mapping:   –  Greedy  search   Dr. Le Dung Hanoi University of Science and Technology Subject Graph Phases  of  synthesis  (3/3)   d   a   c   b   e   f  g   h   •  Technology  mapping:        -­‐    Greedy  search   Dr. Le Dung Hanoi University of Science and Technology Subject Graph 9/25/13 20 •  Technology  mapping:   –  Using  principle  of  op:mality   Phases  of  synthesis  (3/3)   d   a   c   b   e   f  g   h   15   Dr. Le Dung Hanoi University of Science and Technology Subject Graph Phases  of  synthesis  (3/3)   d   a   c   b   e   f  g   h   15    9     •  Technology  mapping:   –  Using  principle  of  op:mality   Dr. Le Dung Hanoi University of Science and Technology Subject Graph 9/25/13 21 Phases  of  synthesis  (3/3)   d   a   c   b   e   f  g   h   •  Technology  mapping:   –  Using  principle  of  op:mality   Dr. Le Dung Hanoi University of Science and Technology Subject Graph Sea of gates Cell I/O buffer Fixed transistor layer Customized metal layer for connecting gate Dr. Le Dung Hanoi University of Science and Technology Gate  array  based  design   + A gate array or uncommitted logic array (ULA) circuit is prefabricated with a number of unconnected logic gates (cells). + CMOS transistors with fixed length and width are placed at regular predefined positions and manufactured on a wafer, usually called a master slice ( sea of gates). + Creation of a circuit with a specified function is accomplished by adding a final surface layer or layers of metal interconnects to the chips on the master slice late in the manufacturing process, joining these elements to allow the function of the chip to be customized as desired  reducing the designing time  reducing the mask costs + Disadvantages - slow clock speed - wasted chip area 9/25/13 22 Dr. Le Dung Hanoi University of Science and Technology Gate  array  based  design  flow   Design  entry   Placement   Rou:ng   Simula:on   Timing  simula:on   Fabrica:on  (metal  1  mask)   Tes:ng   Library of cells Technology  mapping   Dr. Le Dung Hanoi University of Science and Technology Programmable  Device  Based  Design   Based on programmable devices: The interconnection layers are personalized by electronic means for a specific application. This work usually can be done by end-users. F0 = A’B’+ AC’ F1 = B + AC’ F2 = A’B’+ BC’ F3 = AC + B 9/25/13 23 Dr. Le Dung Hanoi University of Science and Technology Programmable  Elements   + Fuse + Antifuse + Switch + Volatile + Non-volatile + One Time Programmable + Reprogrammable (Memory-based) Dr. Le Dung Hanoi University of Science and Technology Programmable  Devices   •  Simple Programmable Logic Device: + Programmable read only memory (PROM) + Field Programmable logic array (FPLA or PLA) + Programmable array logic (PAL) + Generic array logic (GAL) •  Complex programmable logic device (CPLD) •  Field programmable gate array (FPGA) •  Field programmable interconnect (FPIC) 9/25/13 24 Dr. Le Dung Hanoi University of Science and Technology Basic  SPLD  organiza:on     AND array OR array Output options Product terms Sum terms Feedback terms Inputs Outputs Dr. Le Dung Hanoi University of Science and Technology Fuse-­‐based  programmable  AND  –  OR  Array       9/25/13 25 Dr. Le Dung Hanoi University of Science and Technology Output  Polarity  Op:ons     Dr. Le Dung Hanoi University of Science and Technology Bidirec:onal  Pins  and  Feedback  line     9/25/13 26 Dr. Le Dung Hanoi University of Science and Technology PLD  Design  Process     Dr. Le Dung Hanoi University of Science and Technology Combina:onal  Circuit  is  implemented  on  SPLD     9/25/13 27 Dr. Le Dung Hanoi University of Science and Technology PROM  =  Read-­‐Only-­‐Memory   Dr. Le Dung Hanoi University of Science and Technology PROM  =  PLD  with  fixed  AND  array   9/25/13 28 Dr. Le Dung Hanoi University of Science and Technology Full-­‐adder  on  PROM     Dr. Le Dung Hanoi University of Science and Technology PAL   9/25/13 29 Dr. Le Dung Hanoi University of Science and Technology Combina:onal  Circuit  is  implemented  PAL   Dr. Le Dung Hanoi University of Science and Technology FPLA   Programmable OR array Programmable AND array 9/25/13 30 Dr. Le Dung Hanoi University of Science and Technology Combina:onal  Circuit  is  implemented  on  FPLA  (1)   Minimize  each  func:on  separately     8  product  terms   F1  =  bd  +  b’c  +  ab’   F2  =  c  +  a’bd   F3  =  bc  +  ab’c’+  abd   Mul:ple-­‐Output  Op:miza:on     5  product  terms   F1  =  abd  +  a’bd  +  ab’c’+  b’c   F2  =  a’bd  +  b’c  +  bc   F3  =  abd  +  ab’c’+  bc   Dr. Le Dung Hanoi University of Science and Technology Combina:onal  Circuit  is  implemented  on  FPLA  (2)   F1  =  abd  +  a’bd  +  ab’c’+  b’c   F2  =  a’bd  +  b’c  +  bc   F3  =  abd  +  ab’c’+  bc   9/25/13 31 Dr. Le Dung Hanoi University of Science and Technology Exercise   Implement the two functions with PLA PLA Dr. Le Dung Hanoi University of Science and Technology Generic  Array  Logic  architecture   Output logic macrocell (OLMC) 9/25/13 32 Dr. Le Dung Hanoi University of Science and Technology CPLD  architecture   AND-OR Plane O I/O Switch matrix I/O O AND-OR Plane AND-OR Plane O I/O I/O AND-OR Plane O Dr. Le Dung Hanoi University of Science and Technology FPGA  architecture  (1)   9/25/13 33 Dr. Le Dung Hanoi University of Science and Technology FPGA  architecture  (2)   Dr. Le Dung Hanoi University of Science and Technology FPGA  architecture  (3)   Switch Matrix and interconnection Long lines : -  Across whole chip -  High fan-out, low skew -  Suitable for global signals (CLK) and buses -  2 tri-states per CLB for busses 9/25/13 34 Dr. Le Dung Hanoi University of Science and Technology FPGA  architecture  (4)   Configurable Logic Block (CLB) 5 logic inputs Data input (DI) Clock (K) Clock enable (EC) Direct reset (RD) 2 outputs (X,Y) Dr. Le Dung Hanoi University of Science and Technology FPGA  architecture  (5)   I/O Block (IOB) 9/25/13 35 Dr. Le Dung Hanoi University of Science and Technology FPGA  development  toolkit