Charge trapping characterization methodology for the evaluation of hafnium-Based gate dielectric film systems

tacks [10]. Figure 6.7 illustrates representative single pulse Id-Vg characteristics for: a) NH3 700°C, b) N2 800°C, and c) N2O 800°C PDAs where increased charge trapping is seen as bias goes further into inversion. DC Id-Vg is shown for comparison where degradation due to charge trapping from a slower measurement can be seen. In Figure 6.8a and Figure 6.8b, comparisons of ∆Vt at different charging times for various PDA conditions using pulsed Id-Vg (Figure 6.7) to determine ∆Vt at 50% of maximum Id are shown. Fast transient analysis shows the NH3 and 114 N2 800°C PDAs can have significant amount of trapped charge. The N2O 800°C annealed gate stacks show reduced amounts of trapped charge due to increased interfacial layer thickness that reduces the tunneling of electrons to the bulk silicate trap sites. 0.0 0.5 1.0 1.5 2.0 2.5 0 20 40 60 80 100 120 140 160 b) N 2 8 00 oC P DA D ra in C ur re nt [µA ] Gate Voltage [V] 0.0 0.5 1.0 1.5 2.0 2.5 0 20 40 60 80 100 120 140 160 c) N 2O 80 0 oC PDA D ra in C ur re nt [µA ] Gate Voltage [V] 0.0 0.5 1.0 1.5 2.0 2.5 0 20 40 60 80 100 120 140 160 Vg Pulse Height -1 to 1 V -1 to 1 .5 V -1 to 2 V -1 to 2 .2 V t r, PW, t f = 100µs DC Id-Vg NH3 700 oC PDA nFET W/L = 10/1 µm Vd = 40mV Dr ai n C ur re nt [µA ] Gate Voltage [V] PW t r t f PW tr tf ∆Vt a) Figure 6.7. Examples of pulsed Id-Vg characteristics showing increased charge trapping with increasing inversion bias for 100 µs rise, fall, and pulse width times. DC Id-Vg is shown for comparison. 115 10-6 10-5 10-4 10-3 10-3 10-2 10-1 10-3 10-2 10-1 Detection Limit Vg = 1.5 V ∆V t [ V] Charging Time [sec] b) a) Detection Limit Vg = 2 V ∆V t [ V] NH3 700 oC N2 700 oC N2O 700 oC N2 800 oC N2O 800 oC Figure 6.8. Comparison of ∆Vt at different charging times for various PDAs using pulsed Id-Vg (Figure 9) to determine ∆Vt at 50% of the maximum Id for a) Vg = 2 V and b) Vg = 1.5 V. 6.3.5 Pulsed Id-Vg Mobility Extraction The 4 Torr silicates were further studied to determine the impact of the trapped charge on the mobility using the fast transient mobility extraction technique discussed in Chapter 5 [11]. Figure 6.9 shows “trap free” inversion charge compared with split CV, which includes the trapped charge as well as the inversion charge. Comparisons of electron mobility from FT/CP and DC ramp (see Figures 6.2 and 6.3) measurements for NH3 700°C and N2 800°C PDAs are shown in Figure 6.10 and Figure 6.11. The insets illustrate a comparison of pulsed Id-Vg 116 to DC Id-Vg for the mobility values shown. Since the DC mobility extraction technique includes trapped charge, Qinv is larger than it should be while the gd is degraded due to the reduced DC Id (Figures 6.10 and 6.11 insets). Using the above methodology, a “trap-free” Qinv for the “trap-free” gd produces a higher µeff. So, if transistors in logic circuits were able to turn on and off at fast rates (i.e., high frequencies), high-κ gate dielectrics would be useful. Unfortunately, some transistors in circuits could be in the “on” state for a relatively longer time allowing for charge trapping to occur and, therefore, degrade the effective electron mobility. 0.0 0.5 1.0 1.5 2.0 0 5 10 15 4T with NH3 700 oC PDA N in v, N t [ 10 12 /c yc le *c m 2 ] Vgate or Vtop [V] Split CV with trapped charge Inversion Charge Pumping: 100kHz Trap-Free inversion charge Trapped charge Figure 6.9. "Trap free" inversion charge compared with split CV where trapped charge is not removed. 117 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0 50 100 150 200 250 300 350 400 450 500 0.0 0.5 1.0 1.5 2.0 0 20 40 60 80 100 120 140 NH3 700 oC PDA nFET W/L = 10/1 µm Vd = 40mV Pulsed Id-Vg (100kHz) DC Id-Vg D ra in C ur re nt [µA ] Gate Voltage [V] DC Mobility Pulsed Mobility Universal Ef fe ct iv e M ob ili ty [c m 2 /V *s ec ] Effective Field [MV/cm] Figure 6.10. Comparison of electron mobility from pulsed/CP methodology and DC ramp (see Figures 2 and 3) measurements for NH3 700°C PDA. Inset: comparison of pulsed Id-Vg to DC Id-Vg for the mobility shown. 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0 50 100 150 200 250 300 350 400 450 500 0.0 0.5 1.0 1.5 2.0 0 20 40 60 80 100 120 140 N2 800 oC PDA nFET W/L = 10/1 µm Vd = 40mV Pulsed Id-Vg (100kHz) DC Id-Vg D ra in C ur re nt [µA ] Gate Voltage [V] DC Mobility Pulsed Mobility Universal Ef fe ct iv e M ob ili ty [c m 2 /V *s ec ] Effective Field [MV/cm] Figure 6.11. Comparison of electron mobility from pulsed/CP methodolgy and DC ramp (see Figures 2 and 3) measurements for N2 800°C PDA. Inset: comparison of pulsed Id-Vg to DC Id-Vg for the mobility shown. 118 6.4 Summary MOCVD 20% SiO2 Hf silicate deposited at 4 Torr with a chemical oxide interfacial layer produces higher mobility values than 2 Torr silicates that were subjected to the same processing. The N2O PDA increases the thickness of the interfacial oxide, and the NH3 PDA incorporates more nitrogen according to SIMS. From CP, when the charge time is held constant and the discharge time is increased by varying the duty cycle, the Nt values are higher suggesting that more time is required to de-trap than to trap. With a 50% duty cycle of a given frequency, fixed-amplitude CP and fixed-base variable amplitude CP show quite low interface state trap densities (1-3E10/cycle·cm2) for a chemical oxide interfacial layer, and large high-κ bulk trap densities (0.7-3E11/cycle·cm2). Using fast transient measurements and analysis, NH3 700°C and N2 800°C PDAs exhibit significant amounts of trapped charge, but DC mobility is higher in the peak and high field regime while retaining an ~1.6 nm EOT as compared to the N2 700°C PDA. Furthermore, free-carrier mobility extractions for these two anneals indicate that the “intrinsic” mobility, after correcting for the trapped charge, is quite close to the universal electron mobility curve in the high field regime. 119 6.5 References [1] International Technology Roadmap for Semiconductors, 2001. [2] R. M. Wallace and G. Wilk, "High- κ gate dielectric materials," MRS Bulletin, vol. 27, pp. 192-7, 2002. [3] Y. Kim, C. Lim, C. D. Young, K. Matthews, J. Barnett, B. Foran, A. Agarwal, G. A. Brown, G. Bersuker, P. Zeitzoff, M. Gardner, R. W. Murto, L. Larson, C. Metzner, S. Kher, and H. R. Huff, "Conventional Poly-Si Gate MOS-transistors With a Novel, Ultra-Thin Hf-oxide Layer," presented at VLSI Technology Symposium, Kyoto, Japan, 2003. [4] M. V. Fischetti, D. A. Neumayer, and E. A. Cartier, "Effective electron mobility in Si inversion layers in metal-oxide-semiconductor systems with a high-κ insulator: The role of remote phonon scattering," Journal of Applied Physics, vol. 90, pp. 4587- 4608, 2001. [5] T. Yamaguchi, R. Iijima, T. Ino, A. Nishiyama, H. Satake, and N. Fukushima, "Additional Scattering Effects for Mobility Degradation in Hf-silicate Gate MISFETs," presented at International Electron Device Meeting, Washington, DC, 2002. [6] J. R. Hauser and K. Ahmed, "Characterization of Ultrathin Oxides Using Electrical C-V and I-V Measurements," presented at Characterization and Metrology for ULSI Technology: 1998 International Conference, 1998. [7] C. G. Sodini, T. W. Ekstedt, and J. L. Moll, "Charge accumulation and mobility in thin dielectric MOS transistors," Solid State Electronics, vol. 25, pp. 833-41, 1982. [8] J. R. Hauser, "Extraction of experimental mobility data for MOS devices," IEEE Transactions on Electron Devices, vol. 43, pp. 1981-1988, 1996. [9] A. Kerber, E. Cartier, L. Pantisano, R. Degraeve, T. Kauerauf, Y. Kim, A. Hou, G. Groeseneken, H. E. Maes, and U. Schwalke, "Origin of the threshold voltage instability in SiO2/HfO2 dual layer gate dielectrics," IEEE Electron Device Letters, vol. 24, pp. 87-89, 2003. [10] A. Kerber, E. Cartier, L. Pantisano, M. Rosmeulen, R. Degraeve, T. Kauerauf, G. Groeseneken, H. E. Maes, and U. Schwalke, "Characterization of the Vt-instability in SiO2/HfO2 Gate Dielectrics," presented at International Reliability Physics Symposium, Dallas, Texas, 2003. [11] A. Kerber, E. Cartier, L. A. Ragnarsson, M. Rosmeulen, L. Pantisano, R. Degraeve, T. Kauerauf, Y. Kim, and G. Groeseneken, "Direct Measurement of the Inversion Charge in MOSFETs: Application to Mobility Extraction in Alternative Gate Dielectrics," presented at VLSI Technology Symposium, Kyoto, Japan, 2003. 120 7 CHARGE TRAPPING MODEL FOR MOCVD HAFNIUM-BASED GATE DIELECTRIC STACK STRUCTURES AND ITS IMPACT ON DEVICE PERFORMANCE 7.1 Introduction In order to meet the International Technology Roadmap for Semiconductors (ITRS) requirements for equivalent oxide thickness (EOT) and gate leakage current, the conventional SiOxNy gate dielectric will need to be replaced by higher dielectric constant materials [1]. Hafnium-based dielectrics are being widely investigated as potential candidates for the gate dielectric material [2, 3]. Threshold voltage instability and mobility degradation, however, have been identified as significant issues for Hf-based materials [4-8]. To continue to address these issues and those from the previous chapter, we investigated the electrical properties of samples referred to as hybrid stacks (HfO2/Hf Silicate) of various thickness with respect to charge trapping. The impact of charge trapping on device performance was characterized by conventional DC measurements, fixed-amplitude (FA) variable base and fixed-base variable amplitude (VA) charge pumping (CP) [6], Secondary Ion Mass Spectroscopy (SIMS), high resolution Transmission Electron Microscopy (HRTEM), and fast transient (FT) measurements [7, 8]. 121 7.2 Process Flow and Experiment Transistors were fabricated on 200 mm (100) p/p+ epitaxial wafers using a standard NMOS process flow – self-aligned, a-Si gate and 1000°C, 10 sec source/drain activation. In this study, MOCVD hybrid stacks were deposited on ozone (O3) cleaned substrates [3]. The hybrid stack was formed by two consecutive depositions under vacuum conditions where an HfO2 layer (of 1.5 nm, 2.0 nm, and 3.0 nm nominal thickness) was followed by a 1.5 nm 20% SiO2 Hf silicate layer (top Hf silicate layer improves high-κ/polysilicon interface, Figure 7.1). All hybrid stacks received an NH3 post deposition anneal (PDA) at 700°C for 60 sec. A brief summary of the electrical results collected on the W/L=20/20 µm 30Å HfO2 20Å HfO2 15Å HfO2 15Å HfSixOy 15Å HfSixOy 15Å HfSixOy 30/15 Hybrid Si Substrate SiO2 IL 10Å 20/15 Hybrid 15/15 Hybrid Figure 7.1. Schematic representation of the gate stacks in Table I. 122 Table 7.1. Parameters extracted from NCSU CVC and DC measurements for MOCVD hybrid gate stacks [9]. ID 1st High - κ 2nd High - κ EOT [nm] Vfb [V] Jg (Vfb–1) [-A/cm2] 1 HfO2 30 Å 1.45 -0.853 4.87E-03 2 HfO2 20 Å 1.36 -0.831 1.61E-01 3 HfO2 15 Å HfSixOy 15 Å 1.39 -0.819 2.05E-01 transistors is presented in Table 7.1. The NCSU CVC model [9] was used to extract Vfb and EOT from the C-V data. Conventional 100kHz split C-V [10] and NCSU Mob2d [11] mobility extractions were also carried out on these samples. On short channel transistors (W/L = 10/1 µm), fixed amplitude (FA) charge pumping (CP) and variable amplitude (VA) CP were also performed to investigate the gate stack interface (Nit) and bulk (Nt) trapping, respectively. Pulsed Id-Vg measurements were done on the same devices to examine the fast transient characteristics of the hybrid stacks. 7.3 Results and Discussion In an effort to characterize trapped charge in MOCVD hafnium-based gate dielectric stack structures, the “hybrid” stack was subjected to physical and electrical analysis. 123 7.3.1 Physical Analysis High Resolution Transmission Electron Micrograph (HRTEM) images were collected on the hybrid stack samples. Figure 7.2 of the HRTEM images for the 30/15 and 15/15 hybrid stacks shows a similar thickness of an interfacial oxide of 1 nm adjacent to the silicon substrate. To investigate the hybrid stack further, Secondary Ion Mass Spectroscopy (SIMS) was also done (Figure 7.3). The SIMS profiles done after the wet etch removal of the poly electrode suggests that the 20/15 and 15/15 samples are quite similar. 30/15 Hybrid 15/15 Hybrid Figure 7.2. HRTEM images of the 30/15 (left) and 15/15 (right) hybrid stacks. Note that the interfacial oxide layer as about 1 nm in both samples. 124 2 4 6 8 100 2 4 6 8 10 100 101 102 103 104 105 (b) HfO2 Signal Depth [nm] SiO2 Signal 30/15 Hybrid 20/15 Hybrid 15/15 Hybrid C ou nt s pe r S ec on d (a) Figure 7.3. SIMS profiles of hybrid films following wet etch removal of the poly electrode where the 20/15 and 15/15 hybrid stacks are quite similar. 7.3.2 Electrical Analysis 7.3.2.1 DC Measurements The effect of the high-κ physical thickness was initially investigated with conventional DC characterization methodologies using the Keithley 4200 SCS. A brief summary of the electrical results collected on W/L = 20/20 µm transistors is presented in Table 7.1. The EOT and flatband voltage, Vfb, were extracted using NCSU CVC for CV measurements taken at 100 kHz. The 30/15 hybrid has a larger EOT while the 20/15 and 15/15 hybrids have lower and similar EOTs which seem to be supported by the physical analysis. For 125 mobility extraction, split CV and Id-Vg measurements were made. Figure 7.4 shows the inversion capacitance, Cinv, where the thinner hybrids have a small decrease in the capacitance equivalent thickness, CETinv, which is defined as: inv inv C ACET ε= (7.1) where ε is the dielectric constant of SiO2 (3.9·εo), and A is the area. Figure 7.5 shows Id-Vg characteristics where it can be seen that the thickest high-κ stack has the lowest drive current. Although the difference is subtle in the inversion capacitance since EOT values are similar, a significant difference can be seen in the Id-Vg curves. This is mainly attributed to a lower mobility (Figure 7.6). The entire 30/15 hybrid mobility curve is significantly lower than the thinner hybrid stacks. This relative reduction in mobility is interpreted to be caused by the inversion carrier loss due to electron trapping in the thicker gate stack. To verify this, Id-Vg sweeps were taken from –1 to 2 V and 2 to –1 V. As shown in Figure 7.7, when sweeping the gate voltage from 2 to –1 V, a significant Vt shift can be seen for the 30/15 case, and then de-traps as the measurement sweeps back to an accumulation voltage of –1 V. 126 -0.5 0.0 0.5 1.0 1.5 2.0 0 1 2 3 4 5 6 7 8 9 Split CV nFET W/L = 20/20µm Freq = 100 kHz 15/15 Hybrid 20/15 Hybrid 30/15 Hybrid C ap ac ita nc e [p F] Gate Voltage [V] Figure 7.4. Conventional split C-V data showing a small decrease in CETinv as the physical thickness of the high-κ is reduced. 0.0 0.5 1.0 1.5 2.0 0 2 4 6 8 10 12 14 nFET W/L = 20/20µm Vd = 40mV 30/15 Hybrid 20/15 Hybrid 15/15 Hybrid D ra in C ur re nt [µ A ] Gate Voltage [V] Figure 7.5. DC Id-Vg data showing an increase in drive current as the physical thickness of the high-κ is reduced. 127 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0 50 100 150 200 250 300 Ef fe ct iv e M ob ili ty [c m 2 /V *s ec ] Effective Field [MV/cm] 30/15 Hybrid 20/15 Hybrid 15/15 Hybrid Universal Figure 7.6. Electron mobility extracted with the split C-V methodology. Thinner high-κ stacks resulted in higher mobility. 0.0 0.5 1.0 1.5 2.0 0 2 4 6 8 10 down 30/15 Hybrid nFET W/L = 20/20 µm Vg Sweep Direction -1 to 2 V 2 to -1 V D ra in C ur re nt [µ A ] Gate Voltage [V] shifted up-sweep up Figure 7.7. DC Id-Vg data showing a ∆Vt shift when sweeping the gate voltage –1 V → 2 V → –1 V. De-trapping as the down trace returns to –1 V can be seen. 128 7.3.2.2 Charge Pumping Charge-pumping measurements are widely used to characterize interface state densities in MOSFET devices [12]. These measurements can also be performed at different frequencies, so that the frequency response of the traps can be obtained as outlined in Chapter 5 [6]. For high-κ gate stack structures, this CP technique can quantify the bulk trapped charge, Nt. FA CP was executed at 1 MHz with a fixed amplitude of 1.2 V and tr = tf = 100 ns. The results in Figure 7.8 show that the three stacks exhibit ~ 3.5E10/cycle·cm2 demonstrating low Nit values for all stacks evaluated. In the VA CP measurements, tr and tf were also set to 100 ns while the frequency was 100 kHz with the base level fixed at –1 V and the variable amplitude stepped by 50 mV up to 2 V (Figure 7.8). According to VA CP data, the 30/15 stack traps are more efficiently filled at lower voltages, below Vtop ~1.25 V, while at higher voltages the thinner stacks show higher recombination current, Icp. An explanation of this is shown in Figure 7.9 where the device inversion (INV) and accumulation (ACC) states influence the measured CP current (Icp). When the device is in the “ACC” state of the pulse cycle (Vbase = -1), the gate leakage component is added to the measured ICP. However, this contribution does not have a significant impact on the Nt calculation of VA CP into inversion. In the “INV” state of the pulse cycle, the scaled hybrids exhibit a higher source/drain (S/D) leakage from the junctions to the gate, which indirectly enhances Icp due to enhanced injection into the high-κ film. This explanation is supported by the fact that if this leakage went through the gate and did not get trapped, there would be a reduction in the measured Icp as the frequency decreases. 129 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 1010 1011 1012 Fixed Amplitude CP Vamp = 1.2 V Vbase = -1.5 to 0 V Freq = 1 MHz tr, tf = 100ns Variable Amplitude CP Vbase = -1 V Vtop = -1 to 2 V Freq = 100kHz tr, tf = 100ns N it or N t [ #/ cy cl e* cm 2 ] Vbase [V] or Vtop [V] 30/15 Hybrid 20/15 Hybrid 15/15 Hybrid Figure 7.8. Interface (Nit) and bulk (Nt) trapping data for the different hybrid stacks obtained with FA CP and VA CP, respectively. 130 Icp I(d,g)I(s,g) Ig ACC. Icp I(d,g)I(s,g) INV. -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 0.0 1.0x10-8 2.0x10-8 3.0x10-8 4.0x10-8 5.0x10-8 6.0x10-8 7.0x10-8 8.0x10-8 9.0x10-8 1.0x10-7 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 10-15 10-14 10-13 10-12 10-11 10-10 10-9 10-8 10-7 10-6 Variable Amplitude CP Vbase = -1 V Vtop = -1 to 2 V Freq = 100kHz tr, tf = 100ns I S /D o r I cp [A ] Vtop [V] 1 MHz 100 kHz 10 kHz closed symbols: S/D Leakage open symbols: Icp I S/ D o r I cp [A ] Vtop [V] ON OFF 20/15 Hybrid Figure 7.9. In the accumulation (ACC) state, gate leakage current adds to the Icp at the low amplitudes of the VA CP measurement (Insets: “ACC” and inner log plot). In the inversion (INV) state, DC leakage current flows from S/D to the gate that indirectly enhances Icp due to enhanced injection into the high-κ film. 7.3.2.3 Fast Transient Pulsed Transit Charge Trapping Measurements were done similar to [7]. The measurement conFiguration in Section 5.5, shows the nFET in an inverter circuit where Id is 131 ( ) ⎟⎟⎠ ⎞ ⎜⎜⎝ ⎛ −⋅= L DDD D DD Dd R VV V VVI (7.2) where VDD is 100 mV, VD is the voltage measured at the drain of the nFET, and RL is the load resistance. Measurements were done with tr, tf, and the pulse width (PW) values equally set. For the W/L = 10/1 µm transistor, the load resistance, RL, is 330 Ω. Each single pulse (SP) measurement started and ended at –1 V with the top of the pulse taken to 1, 1.5, 2, and 2.2 V. The difference measured between the Id–Vg curves generated by the up and down swing of Vg reflects the effect of the charge trapping (i.e., ∆Vt). Pulsed Id – Vg data was collected on the hybrid stacks, using different charging times and pulse voltages, seen in Figure 7.10. All the results show that ∆Vt increases as the gate bias pulse increases. A comparison to the conventional DC Id-Vg shows the reduction in drive current with the ‘slower’ measurement due to charge trapping during the measurement. In addition, the ∆Vt shifts increased with the increase in the physical thickness of the hybrid stack. Figure 7.11 summarizes the ∆Vt results with respect to charging time, physical thickness, and pulse heights. 132 0.0 0.5 1.0 1.5 2.0 2.5 0 20 40 60 80 100 120 Vg Pulse Height -1 to 1 V -1 to 1.5 V -1 to 2 V -1 to 2.2 V tr, PW, tf = 100µs DC Id-Vg 30/15 Hybrid nFET W/L = 10/1 µm Vd = 40mV D ra in C ur re nt [µ A ] Gate Voltage [V] a) 0.0 0.5 1.0 1.5 2.0 2.5 0 20 40 60 80 100 120 140 160 b) Vg Pulse Height -1 to 1 V -1 to 1.5 V -1 to 2 V -1 to 2.2 V tr, PW, tf = 100µs DC Id-Vg 20/15 Hybrid nFET W/L = 10/1 µm Vd = 40mV D ra in C ur re nt [µ A ] Gate Voltage [V] PW tr tf PW tr tf ∆Vt 0.0 0.5 1.0 1.5 2.0 2.5 0 20 40 60 80 100 120 140 c) Vg Pulse Height -1 to 1 V -1 to 1.5 V -1 to 2 V -1 to 2.2 V tr, PW, tf = 100µs DC Id-Vg 15/15 Hybrid nFET W/L = 10/1 µm Vd = 40mV D ra in C ur re nt [µ A ] Gate Voltage [V] Figure 7.10. Pulsed Id-Vg characteristics for a) 30/15, b) 20/15, and c) 15/15 hybrid stacks with different inversion bias pulses with 100 µs rise, fall, and pulse width times. DC Id-Vg is shown for comparison in each case. 133 7.3.3 High-κ Bulk Trapping To address a critical issue of the location of the trapped charge – bulk of the high-κ film or the interface of the high-κ film with the sub-oxide interfacial layer (IL) – we estimated whether the observed ∆Vt shifts can be explained by the charge trapping exclusively at the high-κ/oxide interface. If only these interface traps are responsible for the electron 3.0 3.5 4.0 4.5 3.0 3.5 4.0 4.53.0 3.5 4.0 4.5 0.0 0.1 0.2 0.3 0.4 0.5 0.6 Vg = 2 V High-κ Physical Thickness [nm] Q' DT = 2 .12 0E- 9 Q'DT = 2.415 E-10 Q'DT = 1.397E-10 Q' DT = 2.4 15E -9 Vg = 2.2 V Vg = 1.5 V ∆V t [ V] Charging Time 5µs 10µs 100µs Figure 7.11. ∆Vt values (measured as in Figure 7.10) for different gate biases and charging times vs. gate stack physical thickness. Horizontal dashed lines connect data point of similar ∆Vt obtained with different charging times/physical thickness values. trapping, ∆Vt would be proportional to the injected charge determined by the direct tunneling current (JDT) through the interfacial oxide layer multiplied by the charging time (τ). In this case, the same ∆Vt values in the samples of different thickness in Figure 7.11 should 134 correspond to the same injected charge since, in all types of stacks, the interfacial oxide thickness = 1 nm (Figure 7.2). One needs to take into account that the different physical thickness of the high-κ film will cause a different voltage drop across this interfacial layer. The voltage drop across the interfacial oxide was determined by using the potential balance expression polysoxmsg VVV +++Φ= ψ (7.3) where Φms is the workfunction difference between the polysilicon gate, Φm, and silicon substrate Φs, defined as , Vsm Φ−Φ ox is the voltage drop across the gate dielectric stack, ψs is the surface potential (i.e., band bending), and Vpoly is the voltage drop across the polysilicon gate. NCSU CVC was used to extract the values of C-V parameters from C-V curves measured at 100 kHz on W/L = 20/20 µm transistors. The C-V sweep started in the “discharge” condition (i.e., starting in accumulation) and swept into inversion minimizing charge trapping. A model C-V curve was generated with [15] to compare the results with CVC for Φms, Vox, ψs, and Vpoly. Equation 7.3 was solved for Vox, where Φms was assumed to be ideal. This ideal flatband voltage, Vfb, was compared to the extracted Vfb from CVC. The difference was subtracted from Vox to account for the voltage shift from ideal (i.e., fixed charge). A simplifying assumption for the graded dual layer hybrid stack is to model it as a single layer with a uniform κ-value of 16 (a value between 12 and ~20 for silicates and HfO2, respectively). The conduction band offset of Hf silicate and Hf oxide are governed by the 5d 135 electron states, therefore expected to be the same offset for pure hafnium oxide or silicate (20% SiO2) (Figure 7.12) [16, 17]. Taking this into account, one gets: 21 VVVox += (7.4) where V1 is the voltage drop across the interfacial oxide and V2 is the voltage drop across the high-k. Since CV 1∝ , ratios can be established as follows: 21 VVVox += SiO2 V2 V1 HfSixOy HfO2 Figure 7.12. Band diagram example for a Hf-based gate dielectric on a SiO2 interfacial oxide illustrating voltage drops across the two portions of the gate stack where V2 is based on the assumed uniform dielectric constant. 136 1 2 2 1 1 2 1 1 2 2 2 1 V t t V t t V V phy phy phy phy ε ε ε ε =⇒= (7.5) where ε1 is 3.9·εo, tphy1 is the interfacial oxide (1 nm) thickness, ε2 is 16·εo, tphy2 is the total nominal high-κ stack thickness. From these ratios, the voltages can be determined in terms of the other and subsequently substituted into equation 7.4. This yields 1 2 2 1 1 1 V t t VV phy phy ox ε ε += (7.6) Since the values are know for Vox , ε1, assumed ε2, tphy1 (from TEM), and tphys2 is the nominal high-k thickness, V1 can be solved for and substituted back into equation 7.4 to obtain V2. So, for a given Vg, the voltage drops across the interfacial oxide and high-κ portion can be determined. Now, a direct tunneling calculation across the interfacial layer can be made using the MIS Tunnel Diode expression [18]: ⎟⎟⎠ ⎞ ⎜⎜⎝ ⎛ −Φ−= 2 2 2exp 1 * 2 Vqmt t AJ Box ox DT h (7.7) 137 where A is a constant, tox is the physical thickness of the SiO2 interface, m* is the effective mass of an electron is SiO2, q is the fundamental electronic charge, ħ is Plank’s constant, ΦB is the barrier height of SiO2 to Si substrate, and Vox is the voltage drop across the SiO2 portion. If the injected electrons trap at the high-κ/SiO2 interface, then: τ•=∝∆ DTDTt JQV (7.8) where QDT is the tunneling charge and τ is the charging time. From (7.8), one should expect that similar ∆Vt values (obtained from different samples and charge times) should correspond to similar tunneling charge values. Verification was performed for all cases of similar ∆Vt values (Figure 7.11). For example, Table 6.2 shows Q’DT for two cases demonstrating very similar ∆Vt’s, the 20/15 (3.5nm) at 100 µs sample and the 30/15 (4.5 nm) at 10 µs sample with a stress Vg = 2 V. Expected charges at the high-κ/SiO2 interface are an order of magnitude different while the ∆Vt’s are similar. Table 6.2. Expected charge at the high-κ/SiO2 interface are an order of magnitude different while ∆Vt’s are similar. 3.5 nm @ 100 µs 4.5 nm @ 10 µs τ•∝ JQ' DTDT 2.415E-10 2.120E-9 138 Therefore, various ∆Vt values cannot be explained by high-κ/SiO2 interface trap filling only, leaving the option of bulk trapping in the high-κ to be further investigated. Figure 7.13 provides a plausible bulk-trapping model for the energy band diagram. This model demonstrates the possible capture of the injected electrons as the high-κ thickness increases. 6 5 4 3 2 1 0 -3 -2 -1 0 1 2 3 1.5 nm HfSixOy 3 nm HfO2 1.5 nm HfSixOy 1.5 nm HfO2 V or Φ b [ V] Gate Stack Physical Thickness [nm] Vg = 2V 30/15 Hybrid Bands 15/15 Hybrid Bands Hi-κ/SiO2 Traps Bulk Hi-κ Traps Hi-κ/SiO2 Traps Bulk Hi-κ Traps 1 nm SiO Drawn to scale Figure 7.13. Band diagram for a plausible bulk-trapping model as a function of physical thickness where the possibility of electron trapping from substrate injection increases with increasing physical thickness. Since there could be a concern that the reduction in trapping for thinner hybrid stacks is due to the SiO2 rich layer moving closer to the interfacial oxide layer (see Section 7.3.1) and a non-uniform κ-value in the high-κ portion of the gate stack that impacts the extracted voltage drops, this study was repeated for single layer 20% SiO2 HfSixOy films on a chemical oxide interfacial layer. A value κ=12 was extracted for the single layer 20% SiO2 Hf Silicate 139 (HfSixOy) films of multiple thickness with an interfacial oxide of 0.9 nm (inset Figure 7.14). Figure 7.14 shows that the increase of ∆Vt values as a function of charging time and physical thickness similar to the hybrid stacks, as well as greater ∆Vt values than in hybrid stacks of the same physical thickness. Again, for similar ∆Vt’s, there is an order of magnitude difference in the Q’DT calculation demonstrating that all the trapped charge cannot be solely at the high-κ/IL interface. 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0 1 2 3 4 5 6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 EO T [n m ] Nominal Physical Thickness [nm] HfSixOy (20% SiO2) Interfacial oxide thickness = .9 nm dielectric constant (κ) ~ 12 Q'DT = 3.254E-10Q 'DT = 8.373 E-9 Vg = 2.2V ∆V t [ V] Physical Thickness [nm] Charging Time 5µs 10µs 100µs Figure 7.14. ∆Vt values for different gate biases and charging times vs. gate stack physical thickness for Hf silicate (20% SiO2). Horizontal dashed lines connect data point of similar ∆Vt obtained with different charging times/physical thickness values. 140 7.3.4 Pulsed Id-Vg Mobility Extraction The 20/15 and the 15/15 hybrid stacks were further studied to determine the impact of the trapped charge on the mobility using the fast transient mobility extraction technique discussed in Chapter 5 [8]. Figure 7.15a and 7.15b show the results of this approach for 20/15 hybrid and 15/15 hybrid stacks, respectively. The Figures show an increase in the peak and high field mobility with the high field mobility being quite close to the universal mobility. Thus one can conclude that, for these particular gate stacks, most of the observed mobility degradation is associated with charge trapping effects. 141 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0 50 100 150 200 250 300 350 400 450 500 0.0 0.5 1.0 1.5 2.0 0 20 40 60 80 100 120 140 20/15 Hybrid nFET W/L = 10/1µm Vd = 40mV Pulsed Id-Vg (100kHz) DC Id-Vg D ra in C ur re nt [µA ] Gate Voltage [V] 20/15 Hybrid Stack DC 20/15 Pulsed 20/15 UniversalEf fe ct iv e M ob ili ty [c m 2 /V *s ec ] Effective Field [MV/cm]a) 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0 50 100 150 200 250 300 350 400 450 500 b) 0.0 0.5 1.0 1.5 2.0 0 20 40 60 80 100 120 140 15/15 Hybrid nFET W/L = 10/1µm Vd = 40mV Pulsed Id-Vg (100kHz) DC Id-Vg D ra in C ur re nt [µA ] Gate Voltage [V] 15/15 Hybrid Stack DC 15/15 Pulsed 15/15 UniversalEf fe ct iv e M ob ili ty [c m 2 /V *s ec ] Effective Field [MV/cm] Figure 7.15. Comparison of electron mobility from pulsed/CP method and DC ramp for: a) 20/15 and b) 15/15 hybrid stacks. Insets: comparison of pulsed Id-Vg to DC Id-Vg for the mobilities shown. 142 7.4 Summary Electron trapping data obtained with the pulsed Id-Vg measurements suggests that the trapping occurs mostly in the bulk of the high-κ film rather than only at the interface of the high-κ dielectric and interfacial oxide which leads to less bulk trapping in physically thinner high-κ gate stacks. Carrier mobility of thinner hybrid stacks corrected for the inversion charge loss due to electron trapping is found to approach the universal high field electron mobility. 7.5 References [1] International Technology Roadmap for Semiconductors, 2001. [2] R. M. Wallace and G. Wilk, "High- k gate dielectric materials," MRS Bulletin, vol. 27, pp. 192-7, 2002. [3] Y. Kim, C. Lim, C. D. Young, K. Matthews, J. Barnett, B. Foran, A. Agarwal, G. A. Brown, G. Bersuker, P. Zeitzoff, M. Gardner, R. W. Murto, L. Larson, C. Metzner, S. Kher, and H. R. Huff, "Conventional Poly-Si Gate MOS-transistors With a Novel, Ultra-Thin Hf-oxide Layer," presented at VLSI Technology Symposium, Kyoto, Japan, 2003. [4] M. V. Fischetti, D. A. Neumayer, and E. A. Cartier, "Effective electron mobility in Si inversion layers in metal-oxide-semiconductor systems with a high-κ insulator: The role of remote phonon scattering," Journal of Applied Physics, vol. 90, pp. 4587- 4608, 2001. [5] T. Yamaguchi, R. Iijima, T. Ino, A. Nishiyama, H. Satake, and N. Fukushima, "Additional Scattering Effects for Mobility Degradation in Hf-silicate Gate MISFETs," presented at International Electron Device Meeting, Washington, DC, 2002. [6] A. Kerber, E. Cartier, L. Pantisano, R. Degraeve, T. Kauerauf, Y. Kim, A. Hou, G. Groeseneken, H. E. Maes, and U. Schwalke, "Origin of the threshold voltage 143 instability in SiO2/HfO2 dual layer gate dielectrics," IEEE Electron Device Letters, vol. 24, pp. 87-89, 2003. [7] A. Kerber, E. Cartier, L. Pantisano, M. Rosmeulen, R. Degraeve, T. Kauerauf, G. Groeseneken, H. E. Maes, and U. Schwalke, "Characterization of the Vt-instability in SiO2/HfO2 Gate Dielectrics," presented at International Reliability Physics Symposium, Dallas, Texas, 2003. [8] A. Kerber, E. Cartier, L. A. Ragnarsson, M. Rosmeulen, L. Pantisano, R. Degraeve, T. Kauerauf, Y. Kim, and G. Groeseneken, "Direct Measurement of the Inversion Charge in MOSFETs: Application to Mobility Extraction in Alternative Gate Dielectrics," presented at VLSI Technology Symposium, Kyoto, Japan, 2003. [9] J. R. Hauser and K. Ahmed, "Characterization of Ultrathin Oxides Using Electrical C-V and I-V Measurements," presented at Characterization and Metrology for ULSI Technology: 1998 International Conference, 1998. [10] C. G. Sodini, T. W. Ekstedt, and J. L. Moll, "Charge accumulation and mobility in thin dielectric MOS transistors," Solid State Electronics, vol. 25, pp. 833-41, 1982. [11] J. R. Hauser, "Extraction of experimental mobility data for MOS devices," IEEE Transactions on Electron Devices, vol. 43, pp. 1981-1988, 1996. [12] G. Groeseneken, H. E. Maes, N. Beltran, and R. F. De-Keersmaecker, "A reliable approach to charge-pumping measurements in MOS transistors," IEEE Transactions on Electron Devices, vol. ED-31, pp. 42-53, 1984. [13] S. S. Chung, S.-J. Chen, C.-K. Yang, S.-M. Cheng, S.-H. Lin, Y.-C. Sheng, H.-S. Lin, K.-T. Hung, D.-Y. Wu, T.-R. Yew, S.-C. Chien, F.-T. Liou, and F. Wen, "A Novel and Direct Determination of the Interface Traps in Sub-100nm CMOS Devices with Direct Tunneling Regime (12-16Å) Gate Oxide," presented at VLSI Technology Symposium, Honolulu, Hawaii, 2002. [14] P. Masson, J. L. Autran, and J. Brini, "On the tunneling component of charge pumping current in ultrathin gate oxide MOSFETs," IEEE Electron Device Letters, vol. 20, pp. 92-4, 1999. [15] E. M. Vogel, C. A. Richter, and B. G. Rennex, "A capacitance-voltage model for polysilicon-gated MOS devices including substrate quantization effects based on modification of the total semiconductor charge," Solid-State Electronics, vol. 47, pp. 1589-1596, 2003. [16] P. W. Peacock and J. Robertson, "Band offsets and Schottky barrier heights of high dielectric constant oxides," Journal of Applied Physics, vol. 92, pp. 4712-4721, 2002. [17] G. Lucovsky, B. Rayner, Z. Yu, and J. Whitten, "Experimental determination of band offset energies between Zr silicate alloy dielectrics and crystalline Si substrates by XAS, XPS and AES and ab initio theory: a new approach to the compositional dependence of direct tunneling currents," presented at IEEE International Electron Devices Meeting. San Francisco, CA, USA, Dec. 2002. [18] S. M. Sze, Physics of Semiconductor Devices, 2nd ed: John Wiley & Sons, Inc., 1981. 144 8 CONCLUSIONS In this work, robust characterization techniques were instrumental in evaluating gate dielectric stack structures in an effort to determine if they meet the rigorous device guidelines set by the ITRS. These effective measurements and strategies have established a standardized methodology for electrical characterization of sub – 2 nm EOT gate dielectrics through the use of highly doped substrates for “short loop” capacitors; measurements on multiple areas for precise scaling with area for data validation; and multiple measurements on a given area for reproducibility. In addition, a case study on device structures showed the impact proper device structures have on the development of precision parametrics. Gate leakage becomes a significant issue in sub – 2 nm EOT gate stacks, and algorithms for correcting measured data were demonstrated through meter corrections in C-V measurements. A gate leakage correction for Id-Vg measurements was shown for robust mobility extraction when gate leakage is appreciable. With the need for a high-κ gate dielectric to replace SiO2, devices were fabricated with a Hf – based dielectric deposited by ALD or MOCVD on a chemical oxide interfacial layer. One of the major issues with high-κ integration is charge trapping that produces threshold voltage shifts and mobility degradation. To investigate charge trapping, several measurement methodologies were employed. C – V hysteresis measurements were shown to provide a good qualitative approach to understanding the charge trapping that is occurring. 145 However, C – V hysteresis is subject to the sweep rate and sweep amplitude. As a more standardized approach, a constant voltage stress with interspersed C – V around the flatband voltage was demonstrated. While a more systematic approach, this “stress-and-sense” measurement loses trapped charge in the switching of the measurement equipment (i.e., from voltage stress to C – V) and because the extraction methodology is near the discharge condition of –1 V. Due to the fast charging and discharging of trap sites in the high-κ gate stacks that were evaluated, faster measurements were needed in an attempt to quantify the trapped charge. Charge pumping (CP) was shown to be an excellent process monitoring tool for measuring trapped charge where fixed-amplitude (CP) at high frequencies provides robust characterization of the substrate/dielectric interface and variable-amplitude (CP) allows characterization of the high-κ bulk trapping properties. The fast transient charge trapping measurements provided the best methodology to quantify the trapped charge. The fast transient gate pulse on the MISFET under test in an inverter circuit provided a robust and systematic way to quantify trapped charge. Since CP and first transient measurements are better protocols for measuring trapped charge, they were used to evaluate an experiment that addressed different post deposition anneals (PDA) on the same starting MOCVD Hf silicate starting film deposited at two chamber pressures (2 Torr and 4 Torr). Out of the PDA’s administered, all of the 4 Torr silicate stacks produced higher mobilities than any of the 2 Torr stacks for the same PDA. This was attributed to larger amounts of trapped charge in the 2 Torr stacks as measured by charge pumping. The N2O PDA’s increased the interfacial oxide thickness as shown by SIMS. This leads to improved mobility values for these stacks because the tunneling distance to high-κ trapping sites was increased as a consequence of the 146 thicker interfacial layer. However, large EOTs occurred for the N2O PDA gate stacks which obviously does not help the effort to scale gate dielectric stacks. Two promising PDA’s that require further optimization include NH3 at 700ºC and N2 800ºC. The fast transient technique paired with variable amplitude change pumping provided a way to extract a “trap free” mobility. For some of the MOCVD samples presented herein, the “trap free” mobility was quite close to the universal electron mobility curve in the high field regime. These time- resolved measurements were also instrumental in the development of the bulk trapping model that was proposed. In an effort to explain why the mobility was improved as the high-k physical thickness decreases, it was demonstrated that all of the trapped charge could not be located only at the interface of the high-κ/interfacial layer suggesting trapping in the bulk of the high-κ. This leads to less trapping in physically thinner high-κ gate stacks where it was shown that mobility improved over a thicker high-κ stack. Future work should be directed to finding approaches to minimize charge trapping in high-κ gate dielectrics. This will require work on the deposition techniques themselves to reduce chlorine and carbon contamination in ALD and MOCVD layers, respectively. In addition, an optimized post deposition anneal treatment will also be required. Although not presented here, a metal gate seems to be a requirement to achieve sub-1 nm EOT’s with high-κ gate stacks and needs to be further studied. The characterization techniques in place to continue to evaluate and quantify trapped charge and its effects on the performance of emerging high-κ gate dielectric MIS structures. 147 APPENDIX: PRESENTATIONS AND PUBLICATIONS University and Small Firm Collaboration for Process Development of Advanced Gate Dielectrics C. Young, B. Barnes, S. Castro, E. Condon, K. Koh, M. Schrader, S. Shah, K. Williamson, M. Xu, R. Kuehn, D. Maher, D. Venables, A. Oberhofer, G. Wang, and J. Chen, in the Proceedings of 13th Biennial University/Government/Industry Microelectronics Symposium, (June 2-3, 1999, University of Minnesota, Minneapolis, MN, pp. 64-72) Process Definition for Obtaining Ultra-thin Silicon Oxides Using Full-wafer Electrical and Optical Measurements A. Oberhofer, J. Chen, K. Koh, M. Schrader, S. Shah, R. Venables, C. Young, M. Xu, R. Kuehn, D. Maher and D. Venables, in the MRS Symposium Proceedings on Ultra-thin SiO2 Materials and High-K Dielectrics, (edited by H. Huff, C. Richter, M. Green, G. Lucovsky and H. Hattori) Volume 567, pp. 573-578 1999. Characterization of Ultrathin Oxide Interfaces (Tox < 1 nm) in Oxide-Nitride Stack Formed by Remote Plasma Enhanced Chemical Vapor Deposition Zhigang Wang, Dexter W. Hodge, Shengqiang Wang, Wenmei Li, Chad Young, Robert T. Croswell, John R. Hauser, in the 4th International Symposium: Physics and Chemistry of SiO2 and the Si-SiO2 Interface, at the 197th Meeting of the Electrochemical Society, (edited by H. Z. Massoud, I. Baumvol, M. Hirose, E. H. Poindexter), May 14-18, 2000, Toronto, Canada, pp. 209-216. Revisiting Electrical Characterization Concerns for Sub-2 nm EOT Gate Dielectrics on Silicon Chadwin Young, George A. Brown and Howard R. Huff, at the International Workshop on Device Technology: Alternatives to SiO2 as Gate Dielectrics for Future Si-Based Microelectronics, September 3-5, 2001, Porto Alegre, Brazil, p. 7 Growth of Sub-1 nm EOT Gate Quality ZrO2 and HfO2 Films by MOCVD Using TDEAZ and TDEAH Precursors Avinash K. Agarwal, Chan Lim, Craig Metzner, Shreyas Kher, George A. Brown, Chadwin Young, Robert Murto and Howard Huff at the International Workshop on Device Technology: Alternatives to SiO2 as Gate Dielectrics for Future Si-Based Microelectronics, September 3-5, 2001, Porto Alegre, Brazil, p. 12 148 Ultra-thin Gate-thickness In line Monitoring: Correlation of Thickness Values Extracted from Quantox COS and MOS Capacitor Characteristics Kwame N. Eason, Xiafang Zhang, Bao Vu, Michael Schrader, Chadwin Young, Shweta Shah, Kwangok Koh, Brian Taff, Stephanie Bogle, Dennis Maher, Alain Diebold, and Clive Hayzelden, in the SEMI Technology Symposium (STS) Critical Technologies Conference, Gate Stack Engineering, at SEMICON Southwest 2001, Oct. 2001, Austin, TX, pp. 69-76. Integration of High-k Gate Stack Systems into Planar CMOS Process Flows H.R. Huff, A. Agarwal, Y. Kim, L. Perrymore, D. Riley, J. Barnett, C. Sparks, M. Freiler, G. Gebara, B. Bowers, P.J. Chen, P. Lysaght, B. Nguyen, J.E. Lim, S. Lim, G. Bersuker, P. Zeitzoff, G.A. Brown, C. Young, B. Foran, F. Shaapur, A. Hou, C. Lim, H. Alshareef, S. Borthakur, D.J. Derro, R. Bergmann, L.A. Larson, M.I. Gardner, J. Gutt, R.W. Murto, K. Torres and M.D. Jackson at the International Workshop on Gate Insulator Program, November 1-2, 2001, Tokyo, Japan, pp. 1-10. Conventional n-channel MOSFET Devices Using Single Layer HfO2 and ZrO2 as High-k Gate Dielectrics with Polysilicon Gate Electrode Y. Kim, G. Gebara, M. Freiler, J. Barnett, D. Riley, J. Chen, K. Torres, J.E. Lim, B. Foran, F. Shaapur, A. Agarwal, P. Lysaght, G.A. Brown, C.D. Young, S. Borthakur, H. Li, B. Nguyen, P. Zeitzoff, G. Bersuker, D. Derro, R. Bergmann, R. Murto, A. Hou, H.R. Huff, E. Shero, C. Pomarede, M. Givens, M. Mazanec, and C. Werkhoven, in the Technical Digest of the International Electron Device Meeting, December 2-5,2001, Washington, D.C., pp. 20.2.1-4. High-k Gate Stacks for Planar, Scaled CMOS Integrated Circuits H.R. Huff, A. Hou, C. Lim, Y. Kim, J. Barnett, G. Bersuker, G.A. Brown, C.D. Young, P. Zeitzoff, J. Gutt, P. Lysaght, M.I. Gardner, and R.W. Murto at the Nano and Giga Challenges in Microelectronics, September 10-13, 2002, Moscow, submitted for publication in the Conference Proceedings. Characteristics of ALCVDTM HfO2 grown using a modified Deposition Sequence for High-k Gate Stacks Chan Lim, Yudong Kim, Alex Hou, Jim Gutt, Steven Marcus, Christophe Pomarede, Gennadi Bersurker, Joel Barnett, Chadwin Young, Peter Zeitzoff, George A. Brown, Mark Gardner, Robert W. Murto, and Howard Huff at the ALCVD™ Conference, submitted for publication in the Symposium Proceedings. 149 Effects of Deposition Sequence and Plasma Treatment on ALCVDTM HfO2 n-MOSFET Properties Chan Lim, Yudong Kim, Alex Hou, Jim Gutt, Steven Marcus, Christophe Pomarede, Eric Shero, Henk de Waard, Chris Werkhoven, Lee Chen, Jihane Tamim, Nirmal Chaudhary, Gennadi Bersurker, Joel Barnett, Chadwin Young, Peter Zeitzoff, George A. Brown, Mark Gardner, Robert W. Murto, and Howard Huff, in Physics and Technology of High-k Gate Dielectrics I, ECS PV 2002--28, 83-92 (2002), Metrology Study of Sub 20Å Oxynitride by Corona-Oxide-Silicon (COS) and Conventional C – V Approaches Pui Yee Hung, George A. Brown, Michelle Zhang, Joe Bennett, Husam N. Al-Shareef, Chadwin Young, Chris Oroshiba, and Alain Diebold at the 2002 MRS Spring Meeting, San Francisco, CA, Vol. 716, B2.12, pp. 119-124. Correcting Effective Mobility Measurements for the Presence of Significant Gate Leakage Current P.M. Zeitzoff, C.D. Young, G.A. Brown, and Y.Kim, IEEE Electron Device Letters, Vol. 24, No. 4, April 2003, pp. 275-277. Conventional Poly-Si Gate MOS-Transistors With a Novel, Ultra-Thin Hf-Oxide Layer Y. Kim, C. Lim, C.D. Young, K Matthews, J. Barnett, B. Foran, A. Agarwal, G.A. Brown, G. Bersuker, P. Zeitzoff, M. Gardner, R.W. Murto, L. Larson, C. Metzner, S. Kher, and H.R. Huff at the 2003 Symposium on VLSI Technology Digest of Technical Papers, June 10-12, 2003, Kyoto, Japan, Session 12A-5. High-k Gate Stacks for Planar, Scaled CMOS Intgrated Circuits H.R. Huff, A. Hou, C. Lim, Y. Kim, J. Barnett, G. Bersuker, G.A. Brown, C.D. Young, P.M. Zeitzoff, J. Gutt, P. Lysaght, M. I. Gardner and R.W. Murto, Microelectronic Engineering, 69, numbers 2-4, pp. 152-167 (September 2003) How to Electrically Qualify High-κ Gates Yuegang Zhao, Chadwin D. Young, and George A. Brown, Semiconductor International, vol. 26, 2003, pp. 51-58. 150 Charge Trapping and Mobility Degradation in MOCVD Hafnium Silicate Gate Dielectric Stack Structures C. D. Young, A. Kerber, T. H. Hou, E. Cartier, G. A. Brown, G. Bersuker, Y. Kim, C. Lim, J. Gutt, P. Lysaght, J. Bennett, C. H. Lee, S. Gopalan, M. Gardner, P. Zeitzoff, G. Groeseneken, R. W. Murto, and H. R. Huff, presented at the 203rd Fall Meeting of the Electrochemical Society, Physics and Technology of High-K Gate Dielectrics - II, October 12-16, 2003, Orlando, FL, PV 2003-??, The Electrochemical Society Proceedings Series, Pennington, NJ (2003). Charge Trapping in MOCVD Hafnium-based Gate Dielectric Stack Structures and the Impact on Device Performance Chadwin D. Young, Gennadi Bersuker, George A. Brown, Chan Lim, Pat Lysaght, Peter Zeitzoff, Robert W. Murto, and Howard R. Huff, presented at the Integrated Reliability Workshop, October 20-23, 2004, Lake Tahoe, CA, proceedings volume in press. Charge Trapping Measurements and Their Application to High-κ Gate Stack Evaluation Chadwin D. Young, Gennadi Bersuker, and George A. Brown, presented at the Semiconductor Research Corporation’s Topical Research Conference on Reliability, October 27-28, 2003, Austin, TX. Charge Trapping and Device Performance Degradation in MOCVD Hafnium-based Gate Dielectric Stack Structures Chadwin D. Young, Gennadi Bersuker, George A. Brown, Chan Lim, Pat Lysaght, Peter Zeitzoff, Robert W. Murto, and Howard R. Huff, to be presented at the International Reliability Physics Symposium, April 25-29, 2004, Phoenix, AZ. 151