Điện, điện tử - Chapter 7: Timing generation and measurements
CCR0, CCR1, CCR2 (Compare/Capture Registers) are used to
load the timer count.
• TAR (Timer A Register) is the 16-bit timer register in which the
count start increment/decrements value depends upon the timer
mode settings.
• CCIFG interrupt flag is set when the timer counts to the value
stored in CCR0 register.
• TAIFG interrupt flag is set when the timer count from CCR0 to
zero.
• TASSELx are the bits used to select one of the clock signals.
• IDx bit are used to divide the clock signal applied to timer.
• MCx bits are used select count mode.
• TACLR bit clears the TAR register, clock divider and count
direction (mode)
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Chapter 7
Timing generation and
measurements
7.1 Timer functions
Microcomputer principles and applications
• Stop watch.
• Captures time of external events.
• Creates output waveform.
• Pulse accumulations.
• Creates periodic interrupts.
7.1 Timer functions
Microcomputer principles and applications
Triangle
Sine
Ramp up
Ramp down
Square
Pulse
7.2 MSP430 Timer
Microcomputer principles and applications
• Asynchronous 16-bit timer/counter with four operating modes.
• Selectable and configurable clock source.
• Two or three configurable capture/compare registers.
• Configurable outputs with PWM capability.
• Asynchronous input and output latching.
• Interrupt vector register for fast decoding of all Timer A
interrupts.
7.3 Timer A
Microcomputer principles and applications
Generally MSP430 family contains two categories of timers
• Timer A
• Timer B.
What is the difference between Timer A and Timer B?
Same in operation, but Timer B is more sophisticated than Timer A
and it has many features available than compared with Timer A.
They are:
• Bit-length of the timer is programmable as 8-bit, 10- bit, 12-bit,
16-bit.
• Some Timers in B category have 7 CCR registers whereas the
Timer A contains three capture/compare registers.
• It contains double-buffered CCR register.
• CCR register can be grouped.
7.3 Timer A
Microcomputer principles and applications
How many timers are there in MSP430G2553?
There are two 16-bit timers are available in MSP430G2553,
excluding watch dog timer.
• Timer A0.
• Timer A1.
Each 16-bit timer starts counts from 0 to 0x0FFFF (0 to 65536) and
they operate in four different modes:
• Stop mode - Timer is in halt state or stops the timer.
• Up mode - Timer counts up from zero to value stored in
TACCR0 register (other than 0xFFFF) and roll over to zero after
it reached the count value. Generally this mode used to produce
time delays.
7.3 Timer A
Microcomputer principles and applications
• Continuous mode - it is same as UP mode but here Timer
counts up from zero to maximum value 0xFFFFh and rolls over
to zero after it reached 0xFFFF and keep going.
• Up/Down mode- in this mode time counts up from 0 to TACCR0
register and then counts down back to zero as shown in figure.
It is good for generating PWM’s and driving motors.
7.3 Timer A
Microcomputer principles and applications
TACCR0
0FFFFh
TACCR0
0FFFFh
TACCR0
0FFFFh
Up mode
Continous mode
Up/Down mode
7.3 Timer A
Microcomputer principles and applications
00
01
10
11
Divider
1/2/4/8
16-bit timer
TAR
Clear RC
CCR0
Count
mode EQU0
Set TAIFG
CCR1
CCR2
TACLR
015
TASSELx IDx
Timer clock
MCx
TACLK
ACLK
SMCLK
INCLK
7.3 Timer A
Microcomputer principles and applications
• CCR0, CCR1, CCR2 (Compare/Capture Registers) are used to
load the timer count.
• TAR (Timer A Register) is the 16-bit timer register in which the
count start increment/decrements value depends upon the timer
mode settings.
• CCIFG interrupt flag is set when the timer counts to the value
stored in CCR0 register.
• TAIFG interrupt flag is set when the timer count from CCR0 to
zero.
• TASSELx are the bits used to select one of the clock signals.
• IDx bit are used to divide the clock signal applied to timer.
• MCx bits are used select count mode.
• TACLR bit clears the TAR register, clock divider and count
direction (mode).
7.4 Timer A Output modes
Microcomputer principles and applications
OUTMODE.x Mode Description
000 Output The output signal OUTx is defined by the
OUTx bit. The OUTx signal updates im-
mediately when OUTx is updated.
001 Set The output is set when the timer counts to
the TACCRx value. It remains set until a
reset of the timer, or until another output
mode is selected and affects the output.
010 Toggle/Reset The output is toggled when the timer
counts to the TACCRx value. It is reset
when the timer counts to the TACCR0
value.
011 Set/Reset The output is set when the timer counts
to the TACCRx value. It is reset when the
timer counts to the TACCR0 value.
7.4 Timer A Output modes
Microcomputer principles and applications
OUTMODE.x Mode Description
100 Toggle The output is toggled when the timer
counts to the TACCRx value. The output
period is double the timer period.
101 Reset The output is reset when the timer counts
to the TACCRx value. It remains reset un-
til another output mode is selected and af-
fects the output.
110 Toggle/Set The output is toggled when the timer
counts to the TACCRx value. It is set when
the timer counts to the TACCR0 value.
111 Reset/Set The output is reset when the timer counts
to the TACCRx value. It is set when the
timer counts to the TACCR0 value.
7.4 Timer A Output modes
Microcomputer principles and applications
Example: Timer in Up Mode
TACCR0
0FFFFh
TACCR1
Output mode 1: Set
Output mode 2: Toggle/Reset
Output mode 3: Set/Reset
Output mode 4: Toggle
Output mode 5: Reset
Output mode 6: Toggle/Set
Output mode 7: Reset/Set
EQU0 EQU1 EQU1EQU0 EQU0
TAIFG TAIFG TAIFG Interrupt events
7.5 Timer A interrupts
Microcomputer principles and applications
There are two interrupt flags (CCIFG and TAIFG) and its
corresponding two interrupt vectors (TACCR0 and TAIV) available
for Timers in MSP430.
7.5 Timer A interrupts
Microcomputer principles and applications
Timer block
TACCR0
TAIV
TAIFG
CCR0
CCIFG
CCR1
CCIFG
CCR2
CCIFG
Interrupt vectors
7.6 Timer A registers
Microcomputer principles and applications
TACTL - Timer A Control Register
15 14 1213 11 10 89
7 6 45 3 2 01
rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0)
rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0)
Timer_A clock source select
(INCLK is device-specific and is often assigned to the
inverted TBCLK) (see the device-specific data sheet)
Unused Bits 15-10 Unused
TASSELx Bits 9-8
00 TACLK
01 ACLK
10 SMCLK
11 INCLK
Unused TASSELx
UnusedMCx TACLR TAIE TAIFGMCxIDx
7.6 Timer A registers
Microcomputer principles and applications
TACTL - Timer A Control Register
15 14 1213 11 10 89
7 6 45 3 2 01
rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0)
rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0)
Input divider. These bits select the divider for the input clockIDx Bits 7-6
00
01
10
11
/1
/2
/4
/8
Mode control . Setting MCx = 00h when Timer_A is not in use conserves power.MCx Bits 5-4
00
01
10
11
Stop mode: the timer is halted.
Up mode: the timer counts up to TACCR0.
Continuous mode: the timer counts up to 0FFFFh.
Up/down mode: the timer counts up to TACCR0 then down to 0000h.
Unused TASSELx
UnusedMCx TACLR TAIE TAIFGMCxIDx
7.6 Timer A registers
Microcomputer principles and applications
TACTL - Timer A Control Register
15 14 1213 11 10 89
7 6 45 3 2 01
rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0)
rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0)
Unused Bit 3 Unused
TACLR Bit 2 Timer_A clear. Setting this bit resets TAR, the clock divider, and the count
direction. The TACLR bit is automatically reset and is always read as zero.
TAIE Bit 1 Timer_A interrupt enable. This bit enables the TAIFG interrupt request.
0
1
Interrupt disabled
Interrupt enabled
TAIFG Bit 0 Timer_A interrupt flag.
0
1
No interrupt pending
Interrupt pending
Unused TASSELx
UnusedMCx TACLR TAIE TAIFGMCxIDx
7.6 Timer A registers
Microcomputer principles and applications
TAR - Timer A Register
15 14 1213 11 10 89
7 6 45 3 2 01
rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0)
rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0)
TARx Bits 15-0 Timer_A register. The TAR register is the count of Timer _A.
TARx
TARx
7.6 Timer A registers
Microcomputer principles and applications
TACCRx - Timer A Capture/Compare Register
15 14 1213 11 10 89
7 6 45 3 2 01
rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0)
rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0)
TACCRx Bits 15-0 Timer_A capture/compare register.
Compare mode: TACCRx holds the data for the comparison to the timer
value in the Timer_A Register, TAR.
Capture mode: The Timer_A Register, TAR, is copied into the TACCRx
register when a capture isperformed .
TARx
TARx
7.6 Timer A registers
Microcomputer principles and applications
TACCTLx - Timer A Capture/Compare Control Register
15 14 1213 11 10 89
7 6 45 3 2 01
CCISx
rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) r r0 rw-(0)
rw-(0) rw-(0) rw-(0) rw-(0) r rw-(0) rw-(0) rw-(0)
Capture modeCMx Bits 15-14
00 No capture
01 Capture on rising edge
10
11
CAPCMx
Capture on fallig edge
Capture on both rising and falling edges
Capture/compare input select. These bits select the TACCRx input signal.
See the device-specific data sheet for specific signal connections.
CCISx Bits 13-12
00 CCIxA
01
10
11
CCIxA
GND
Vcc
SCS Bit 11 Synchronize capture source. This bit is used to synchronize the capture
input signal with the timer clock.
0
1
Asynchronous capture
Synchronous capture
UnusedSCCISCS
CCIFGOUTMODx COVOUTCCICCIE
7.6 Timer A registers
Microcomputer principles and applications
TACCTLx - Timer A Capture/Compare Control Register
15 14 1213 11 10 89
7 6 45 3 2 01
CCISx
rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) r r0 rw-(0)
rw-(0) rw-(0) rw-(0) rw-(0) r rw-(0) rw-(0) rw-(0)
Synchronized capture/compare input. The selected CCI input
signal is latched with the EQUx signal and can be read via this bit
SCCI Bit 10
Unused Bit 9 Unused. Read only. Always read as 0.
TACLR Bits 7 - 5 Output mode. Modes 2, 3, 6, and 7 are not useful for TACCR0,
because EQUx = EQU0.
CAPCMx
SCS Bit 8 Capture mode
0
1
Compare mode
Capture mode
000
001
010
011
OUT bit value
Set
Toggle/reset
Set/reset
100
101
110
111
Toggle
Reset
Toggle/set
Reset/set
UnusedSCCISCS
CCIFGOUTMODx COVOUTCCICCIE
7.6 Timer A registers
Microcomputer principles and applications
TACCTLx - Timer A Capture/Compare Control Register
15 14 1213 11 10 89
7 6 45 3 2 01
CCISx
rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) r r0 rw-(0)
rw-(0) rw-(0) rw-(0) rw-(0) r rw-(0) rw-(0) rw-(0)
CAPCMx UnusedSCCISCS
CCIFGOUTMODx COVOUTCCICCIE
CCIE Bit 4 Capture/compare interrupt enable. This bit enables the interrupt request of
the corresponding CCIFG flag.
0
1
Interrupt disabled
Interrupt enabled
CCI Bit 3 Capture/compare input. The selected input signal can be read by this bit.
OUT Bit 2 Output. For output mode 0, this bit directly controls the state of the output .
0
1
Output low
Output high
COV Bit 1 Capture overflow. This bit indicates a capture overflow occurred. COV must
be reset with software.
0
1
No capture overflow occurred
Capture overflow occurred
CCIFG Bit 0 Capture/compare interrupt flag
0
1
No interrupt pending
Interrupt pending
7.6 Timer A registers
Microcomputer principles and applications
TAIV - Timer A Interrupt Vector Register
10 8
r0 r0
9
r0
11
r0
12
r0
13
r0
14
r0
15
r0
2 0
r-(0) r0
1
r-(0)
3
r-(0)
4
r0
5
r0
6
r0
7
r0
00000000
0000 TAIVx 0
TAIV
contents Interrupt Source Interrupt flag Interrupt priority
00h No interrupt pending - Highest
02h Capture/Compare TACCR1 CCIFG -
04h Capture/Compare TACCR2 CCIFG -
06h Reserved - -
08h Reserved - -
0Ah Timer overflow TAIFG -
0Ch Reserved - -
0Eh Reserved - Lowest
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