Điện, điện tử - Chapter 9: Serial communication interface

Chapter 9 Serial communication interface 9.1 USCI Overview Microcomputer principles and applications The universal serial communication interface (USCI) modules support multiple serial communication modes. Different USCI modules support different modes. The USCI_Ax modules support: • UART mode. • Pulse shaping for Infrared Data Association (IrDA) communications. • Automatic baud rate detection for Local Interconnect Network (LIN) communications. • Serial Peripheral Interface (SPI) mode. The USCI_Bx modules support: • Inter-Integrated Circuit (I2C or I2C) mode. • SPI mode. 9.2 UART Mode Microcomputer principles and applications UART = Universal asynchronous receiver/transmitter. UART mode (UCSYNC bit=0) features include: • 7- or 8-bit data with odd, even, or non-parity. • Independent transmit and receive shift registers. • Separate transmit and receive buffer registers. • LSB-first or MSB-first data transmit and receive. • Built-in idle-line and address-bit communication protocols for multiprocessor systems. • Receiver start-edge detection for auto-wake up from LPMx modes. • Programmable baud rate with modulation for fractional baud rate support. • Status flags for error detection and suppression. • Status flags for address detection. • Independent interrupt capability for receive and transmit. 9.3 UART Mode Microcomputer principles and applications • Start - Part of the serial interface’s job is to frame the bits of each data, using a start bit to indicate the start of the data. The start bit then serves to synchronize the sender and the receiver. • Stop - Part of the serial interface’s job is to frame the bits of each data, using a stop bit for the end of the data. • Baud rate - The start bit marks the beginning of the sender’s data. From the start bit the receiver can count clock ticks to determine when to read each data bit. The baud rate defines the time each bit exists or the time to wait between reading (or sending) each bit. • A parity bit (or check bit) - a bit added to the end of a string of binary code that indicates whether the number of bits in the string with the value one is even or odd. Parity bits are used as the simplest form of error detecting code. 9.3 UART Mode Microcomputer principles and applications A start bit (0), 8 bits of data (least significant bit first), and a stop bit (1). This protocol is used for both transmitting and receiving. Start b  b1 b b3 b b5 b b7 StopSerial port One frame 5V 0V 9.3 UART Mode Microcomputer principles and applications Reading the data sent: 1. The receiver waits to detect a start bit 2. Waits 1/(Baud rate) second for the start bit to pass 3. Reads a data bit. 4. Wait 1/(Baud rate) second read another data bit, etc. until all data bits up to the stop bit have been read. 9.4 SPI Mode Microcomputer principles and applications Standard SPI masters communicate with slaves using the serial clock (SCK), Master Out Slave In (MOSI), Master In Slave Out (MISO), and Slave Select (SS) lines. The SCK, MOSI, and MISO signals can be shared by slaves while each slave has a unique SS line. 9.4 SPI Mode Microcomputer principles and applications The USI module is configured in SPI mode when USII2C = 0. Control bit USICKPL selects the inactive level of the SPI clock while USICKPH selects the clock edge on which SDO is updated and SDI is sampled. 9.4 SPI Mode Microcomputer principles and applications 9.4 SPI Mode Microcomputer principles and applications SPI Master Mode The USI module is configured as SPI master by setting the master bit USIMST and clearing the I2C bit USII2C. Since the master provides the clock to the slave(s) an appropriate clock source needs to be selected and SCLK configured as output. When USIPE5 = 1, SCLK is automatically configured as an output. 9.4 SPI Mode Microcomputer principles and applications SPI Slave Mode The USI module is configured as SPI slave by clearing the USIMST and the USII2C bits. In this mode, when USIPE5 = 1 SCLK is automatically configured as an input and the USI receives the clock externally from the master. If the USI is to transmit data, the shift register must be loaded with the data before the master provides the first clock edge. The output must be enabled by setting USIOE. When USICKPH = 1, the MSB will be visible on SDO immediately after loading the shift register. 9.5 I2C Mode Microcomputer principles and applications I2C created by Philips Semiconductors and commonly written as ’I2C’ stands for Inter-Integrated Circuit and allows communication of data between I2C devices over two wires. It sends information serially using one line for data (SDA) and one for clock (SCL). 9.5 I2C Mode Microcomputer principles and applications Master and slave The phillips I2C protocol defines the concept of master and slave devices. A master device is simply the device that is in charge of the bus at the present time and this device controls the clock and generates START and STOP signals. Slaves simply listen to the bus and act on controls and data that they are sent. The master can send data to a slave or receive data from a slave - slaves do not transfer data between themselves. 9.5 I2C Mode Microcomputer principles and applications Multi Master Multi master operation is a more complex use of I2C that lets you have different controlling devices on the same bus. You only need to use this mode if you have more than one microcontroller on the bus (and you want either of them to be the bus master). Multi master operation involves arbitration of the bus (where a master has to fight to get control of the bus) and clock synchronisation (each may a use a different clock e.g. because of separate crystal clocks for each micro). 9.5 I2C Mode Microcomputer principles and applications Data and Clock The I2C interface uses two bi-directional lines meaning that any device could drive either line. In a single master system the master device drives the clock most of the time - the master is in charge of the clock but slaves can influence it to slow it down (See Slow Peripherals below). The two wires must be driven as open collector/drain outputs and must be pulled high using one resistor each - this implements a ’wired AND function’ - any device pulling the wire low causes all devices to see a low logic value - for high logic value all devices must stop driving the wire.