Kỹ thuật viễn thông - Chapter 13: Bit level arithmetic architectures

Chapter 13: Bit Level Arithmetic Architectures Keshab K. Parhi Chap. 13 2 • A W-bit fixed point two’s complement number A is represented as : A=aw-1.aw-2a1.a0 where the bits ai, 0 £ i £ W-1, are either 0 or 1, and the msb is the sign bit. • The value of this number is in the range of [-1, 1 – 2-W+1] and is given by : A = - aw-1 + S aw-1-i2-i • For bit-serial implementations, constant word length multipliers are considered. For a W´W bit multiplication the W most-significant bits of the (2W-1 )-bit product are retained. Chap. 13 3 • Parallel Multipliers : A = aw-1.aw-2a1.a0 = -aw-1 + å - = 1 1 W i aw-1-i2-i B = bw-1.bw-2b1.b0 = -bw-1 + å - = 1 1 W i bw-1-i2-i Their product is given by : P = -p2W-2 + å - = 22 1 W i p2W-2-i2-i In constant word length multiplication, W – 1 lower order bits in the product P are ignored and the Product is denoted as X Ü P = A ´ B, where X = -xW-1 + å - = 1 1 W i xw-1-i2-i Chap. 13 4 • Parallel Multiplication with Sign Extension : Using Horner’s rule, multiplication of A and B can be written as P = A ´ (-bW-1 + S bW-1-i2-i) = -A. bW-1 + [A. bW-2 + [A. bW-3 +[ + [A. b1 + A b0 2-1] 2-1]]2-1] 2-1 where 2-1 denotes scaling operation. • In 2’s complement, negating a number is equivalent to taking its 1’s complement and adding 1 to lsb as shown below: 11 1 11 11 1 11 1 1 1 1 11 1 1 11 22)1()1( 212)1( 22)1( 2 +--- = --- +-- = - --- - = -- = - --- - = - --- +-+--= +--+= --+= -=- å å åå å WiW i iww WW i i iww W i iW i i iww W i i iww aa aa aa aaA Chap. 13 5 • The additions cannot be carried out directly due to terms having negative weight. Sign extension is used to solve this problem. For example, A = a3 + a22-1 + a12-2 + a02-3 = -a32 + a3 + a22-1 + a12-2 + a02-3 = -a322 + a32 + a3 + a22-1 + a12-2 + a02-3 describes sign extension of A by 1 and 2 bits. Tabular form of bit-level array multiplication Chap. 13 6 • Parallel Carry-Ripple Array Multipliers : Bit level dependence Graph Chap. 13 7 Parallel Carry Ripple Multiplier Chap. 13 8 DG for 4´4-bit carry save array multiplication Parallel carry-save array multiplier Chap. 13 9 • Baugh-Wooley Multipliers: Ø Handles the sign bits of the multiplicand and multiplier efficiently. Tabular form of bit-level Baugh-Wooley multiplication Chap. 13 10 • Parallel Multipliers with Modified Booth Recoding : Ø Reduces the number of partial products to accelerate the multiplication process. Ø The algorithm is based on the fact that fewer partial products need to be generated for groups of consecutive zeros and ones. For a group of “m” consecutive ones in the multiplier, i.e., 0{111}0 = 1{000}0 - 0{001}0 = 1{001}0 instead of “m” partial products, only 2 partial products need to be generated is signed digit representation is used. Ø Hence, in this multiplication scheme, the multiplier bits are first recoded into signed-digit representation with fewer number of nonzero digits; the partial products are then generated using the recoded multiplier digits and accumulated. Chap. 13 11 string of 1’s-00111 beginning of 1’s-A-1011 A single 0-A-1101 beginning of 1’s-2A-2001 end of 1’s+2A2110 a single 1+A1010 end of 1’s+A1100 string of 0’s+00000 CommentsOperationb’ib2i-1b2ib2i+1 Radix-4 Modified Booth Recoding Algorithm Recoding operation can be described as: b’i = -2b2i+1 + b2i + b2i-1 Chap. 13 12 Interleaved Floor-Plan and Bit-Plane-Based Digital Filters • A constant coefficient FIR filter is given by: y(n) = x(n) + f·x(n-1) + g·x(n-2) where, x(n) is the input signal, and f and g are filter coefficients. • The main idea behind the interleaved approach is to perform the computation and accumulation of partial products associated with f and g simultaneously thus increasing the speed. • This increases the accuracy as truncation is done at the final step. • If the coefficients are interleaved in such a way that their partial products are computed in different rows, the resulting architecture is called bit-plane architecture. Chap. 13 13 Bit-Serial Multipliers • Lyon’s Bit-Serial Multiplier using Horner’s Rule : • For the scaling operator, the first output bit a1 should be generated at the same time instance when the first input a1 enters the operator. Since input a1 has not entered the system yet, the scaling operator is non-causal and cannot be implemented in hardware. Chap. 13 14 Derivation of implementable bit-serial 2’s complement multiplier Chap. 13 15 Lyon’s bit-serial 2’s complement multiplier Chap. 13 16 Design of Bit-Serial Multipliers Using Systolic Mappings Here, dT = [1 0], sT = [1 1] and pT = [0 1] 01x(-1,1) 10carry(1,0) 10b(1,0) 11a(0,1) sTepTee •Design of Lyon’s bit-serial multiplier by systolic mapping Using DG of ripple carry multiplication. Chap. 13 17 •Design of bit-serial multiplier by systolic mapping using DG of ripple carry multiplication and the following : dT = [0 1], sT = [0 1] and pT = [1 0] 1-1x(-1,1) 01carry(1,0) 01b(1,0) 10a(0,1) sTepTee Chap. 13 18 •Design of bit-serial multiplier by systolic mapping using DG for carry-save array multiplication and the following : dT = [1 0], sT = [1 1] and pT = [0 1] 01x(-1,1) 10carry(1,0) 11b(1,0) 11a(0,1) sTepTee Chap. 13 19 Dependence graph for carry save Baugh-Wooley multiplication with carry ripple vector merging Chap. 13 20 •Design of bit-serial Baugh-Wooley multiplier by systolic mapping using DG for Baugh-Wooley multiplication and the following : dT = [0 1], sT = [0 1] and pT = [1 0] 0-1carry-vm(-1,0) 11x(1,1) 01b(1,0) 10carry(0,1) 10a(0,1) sTepTee Here, carry-vm denotes the carry outputs in the vector merging portion. Chap. 13 21 Bit-Serial Baugh-Wooley Multiplier Chap. 13 22 DG bit-serial Baugh-Wooley multiplier with carry-save array and vector merging portion treated as two separate planes Chap. 13 23 Bit-serial Baugh-Wooley multiplier using the DG having two separate planes for carry-save array and the vector merging portion Chap. 13 24 Bit-Serial FIR Filter Bit-level pipelined bit-serial FIR filter, y(n) = (-7/8)x(n) + (1/2)x(n-1), where constant coefficient multiplications are implemented as shifts and adds as y(n) = -x(n) + x(n)2-3 + x(n-1)2-1. (a)Filter architecture with scaling operators; (b) feasible bit-level pipelined architecture Chap. 13 25 Bit-Serial IIR Filter • Consider implementation of the IIR filter Y(n) = (-7/8)y(n-1) + (1/2)y(n-2) + x(n) where, signal word-length is assumed to be 8. • The filter equation can be re-written as follows: w(n) = (-7/8)y(n-1) + (1/2)y(n-2) Y(n) = w(n) + x(n) which can be implemented as an FIR section from y(n-1) with an addition and a feedback loop as shown below: Chap. 13 26 • Steps for deriving a bit-serial IIR filter architecture: Ø A bit-level pipelined bit-serial implementation of the FIR section needs to be derived. Ø The input signal x(n) is added to the output of the bit- serial FIR section w(n). Ø The resulting signal y(n) is connected to the signal y(n-1). Ø The number of delay elements in the edge marked ?D needs to be determined.(see figure in next page) • For, systems containing loop, the total number of delay elements in the loops should be consistent with the original SFG, in order to maintain synchronization and correct functionality. • Loop delay synchronization involves matching the number of word-level loop delay elements and that in the bit-serial architecture. The number of bit-level delay elements in the bit-serial loops should be W ´ ND, where W is signal word- length and ND denotes the number of delay elements in the word-level SFG. Chap. 13 27 • Bit-level pipelined bit-serial architecture, without synchronization delay elements. (b) Bit-serial IIR filter. Note that this implementation requires a minimum feasible word-length of 6. Chap. 13 28 Note: Ø To compute the total number of delays in the bit-level architecture, the paths with the largest number of delay elements in the switching elements should be counted. Ø Input synchronizing delays (also referred as shimming delays or skewing delays). Ø It is also possible that the loops in the intermediate bit- level pipelined architecture may contain more than W ´ ND number of bit-level delay elements, in which case the word- length needs to be increased. Ø The architecture without the two loop synchronizing delays can function correctly with a signal word-length of 6, which is the minimum word-length for the bit-level pipelined bit- serial architecture. Chap. 13 29 • Associativity transformation : Loop iteration bound of IIR filter can be reduced from one-multiply-two-add to one-multiply-add by associative transformation Chap. 13 30 Bit-serial IIR filter after associative transformation. This implementation requires a minimum feasible word-length of 5. Chap. 13 31 Canonic Signed Digit Arithmetic • Encoding a binary number such that it contains the fewest number of non-zero bits is called canonic signed digit(CSD). • The following are the properties of CSD numbers: Ø No 2 consecutive bits in a CSD number are non-zero. Ø The CSD representation of a number contains the minimum possible number of non-zero bits, thus the name canonic. Ø The CSD representation of a number is unique. Ø CSD numbers cover the range (-4/3,4/3), out of which the values in the range [-1,1) are of greatest interest. Ø Among the W-bit CSD numbers in the range [-1,1), the average number of non-zero bits is W/3 + 1/9 + O(2-W). Hence, on average, CSD numbers contains about 33% fewer non-zero bits than two’s complement numbers. Chap. 13 32 • Conversion of W-bit number to CSD format: – A = a’W-1. a’W-2 a’1. a’0 = 2’s complement number – Its CSD representation is aW-1. aW-2 a1. a0 • Algorithm to obtain CSD representation: – a’-1 = 0; – g-1 = 0; – a’W = a’W-1; – for (i = 0 to W-1) { qi = a’i Å a’i-1; gi = gi-1qi; ai = (1 - 2a’i+1)gi; } Chap. 13 33 -1010-100-10ai -111-1-1-11-1-11 - 2a’i+1 101010010gi 101010011qi 1100111011a’i -10W-1Wi Table showing the computation of the CSD representation for the number 1.01110011. Chap. 13 34 CSD Multiplication A CSD multiplier using linear arrangement of adders to compute x ´ 0.10100100101001 •Horner’s rule for precision improvement : This involves delaying the scaling operations common to the 2 partial products thus increasing accuracy. •For example, x·2-5 + x·2-3 can be implemented as (x·2-2 + x)2-3 to increase the accuracy. Chap. 13 35 Using Horner’s rule for partial product accumulation to reduce the truncation error. Chap. 13 36 Rearrangement of the CSD multiplication of x ´ 0.10100100101001 using Horner’s rule for partial product accumulation to reduce the truncation error. Chap. 13 37 Use of Tree-Height Reduction for Latency Reduction (a) linear arrangement (b) tree arrangement Combination of tree-type arrangement and Horner’s rule for the accumulation of partial products in CSD multiplication Chap. 13 38 Bit serial architecture using CSD. In this case the coefficients -7/32 = -1/4 + 1/32 is encoded as 0.01001 and ¾ = 1 – ¼ is encoded as 1.01.