Phần cứng - Chapter 4: The von neumann model

Chapter 4The Von Neumann Model Basic components Instruction processingNotationsSets of BitsA[3:0] denotes a set of 4 bits: A0, A1, A2, A3The content of an n-bit register R is referred to as R[n-1:0] Rn-1 is the most significant bit (MSB), or leftmost bitR0 is the least significant bit (LSB), or rightmost bitGiven R[31:0], R[7:4] refers to the four bits from R4 to R7Bit AssignmentR[5:0]  I[13:8]Means that bits 5 to 0 of register R get assigned the values of bits 13 to 8 of register I.2The von Neumann Model - 1Memory: holds the instructions and data Processing Unit: processes the informationInput: external information into the memoryOutput: produces results for the userControl Unit: manages computer activityMemoryProcessing UnitInputOutputMARMDRALUTEMPControl UnitPCIR*keyboard*monitor3The von Neumann Model - 2Memory (RAM)Each location has an address and contentsAddress: set of bits that uniquely identify a memory location (eg. 20 bits gives an address space of 220 locations) Addressability (Byte vs. Word):Note: a Word is the basic unit of data used by the processing unit (usually multiple bytes)The size of the memory location referenced by a given addressInput & OutputLC2 deals only with keyboard and monitorMore details later4The von Neumann Model - 3 Processing UnitALU (Arithmetic and Logic Unit)Generally operates on entire words of dataSome also work on subsets of words (eg. bits and bytes)Registers: Small, fast “on-board” storage for wordsClose to the ALU (much faster access than RAM)Control UnitProgram Counter (PC) or Instruction PointerHolds the address of the next instruction to be executedInstruction Register (IR)Holds the instruction being executedThe control unit coordinates all actions needed to execute the instruction5The LC-2 Data and Control Paths6LC 2 InstructionsInstruction word: 16 bitsOpcodedefines (names) the instruction to be executed bits[15:12]: 4 bits allow 16 instructionsOperandsRegisters: 8 registers (i.e. require 3 bits for addressing)Address parameters: Offset (9 bits) or Index (6 bits) (more later)Immediate value: 5 bitsExamplesADD DR, SR1, SR2 ; DR  (SR1) + (SR2) [15:12] [11:9] [8:6] [2:0] - Note: (Reg1) means “content of Reg1”LDR DR, BaseR, Offset ; DR  Mem[BaseR + Offset] [15:12] [11:9] [8:6] [5:0] - Note: Mem[loc] means “content of memory location loc”7Instruction Cycle - 1Six phases (steps)Fetch: load IR with instruction from memoryDecode: determine action to take (which instructions)Evaluate address: compute memory address of operands, if anyFetch operands: read operands from memory or registersExecute: perform instructionStore results: write result to destination (register or memory)8Instruction Cycle - 2FetchThis actually takes several steps, represented here as “micro-instructions”, each of which can take a number of machine cycles to implement:MAR  (PC) ; use the value in PC to access memoryMDR  Mem[MAR] ; read memory location to MDRIR  (MDR) ; move (MDR) to IRPC (PC) + 1 ; increment the value of PCDecodeA decoder reads the opcode bit pattern & sets up the next state of the machine to appropriately use the remaining bits of the instruction. 9Instruction Cycle - 3Evaluate AddressComputes the address of the memory location required to process the instruction (if any): e.g. the location from which to obtain a value. This is known as the Effective Address (EA).Fetch OperandsObtains the source operand(s) (if any) either from Registers or from memory, i.e. from the EA calculated in the previous step.10Instruction Cycle - 4ExecuteCarries out the execution of the instruction - e.g. add two operands present at the input of the ALUStore ResultWrites the result (if any) to its designated destination, either register or memory (using the EA calculated earlier)Start over Recall that the PC was incremented already in the first step, so the next Fetch will bring back the next instruction - unless the instruction just executed changed the PC.11Instruction Cycle - 5Some instructions don't need all 6 phasesIf only using registers, skip Evaluate AddressIf only moving data, skip ExecuteControl InstructionsThese change the sequence of instructionsBranchLoopFunction or procedure callExecute phase changes the content of the PC, so the next instruction will be out of sequence.12Stopping the ComputerOperating System controls the computerwhen a program completes:it exitsit returns control to the operating systemOS is ready for next command or programExternal Controlkill or halt a programreset a computer13The ClockThe Drum Beat of the Computerevery operation happens in multiples of a clock cyclesclockQClockgenerator(crystal)SRRun Latchif the run latch is set (output Q = 1) then the clock output is the same as the clock generatorif the latch is reset (off) then the clock output is disabled0 voltsone clock cycle2.9 voltstime14