Phần cứng - Chapter 5: The LC - 2 instruction set architecture

Chapter 5The LC-2 Instruction Set Architecture Operate instructions Data Movement instructions Control InstructionsISA OverviewMemoryAddress spaceAddressability: Word or ByteRegistersNumberTypeInstructionsOperationsData TypesAddressing Modes2LC-2 Memory Organizationaddressabilityword (16 bits/location)address space216 locations= 64k29 words/page= 51227 pages=128pagelocation in page[8:0][15:9]Address [16:0]3General Purpose Registers (GPRs)RegistersSpecial “memory” that is “inside” the CPUVery fast access: 1 clock cycle.General Purpose Registers: addressable by an instrcution (visible to the user).Other registers may not be accessible (not architectured)LC-28 general purpose registers: R0,R1,...,R7a register can hold any 16 bit pattern - I.e. data or addressesOther special purpose registers (later)4InstructionsTwo main partsOpcode: specifies what the instruction does.Operand(s): what the instruction acts onInstruction sets can be complex or simpleLC-24-bit opcode => 16 instructions up to two sources and one destinationExample: 0 0 0 10 1 10 0 1 0 1 0 0 0 0 ADDR3R1R415 14 13 1211 10 98 7 6 5 2 1 0 4 3 5OperationsOperateManipulate data directlyADD, AND, NOTData MovementMove data between memory and registers (CPU)LD, LDI, LDR, LEA, ST, STI, STRControlChange the sequence of instruction executionBR, JMP/JSR, JMPR/JSSR, RET, RTI, TRAP6Data TypesWhat data types are supported by the computer instructions?Eg. integer, floating point, BCD, character ...LC-2: only 2's complement integersbit strings and addresses are not data types7Condition Codes3 single-bit registers (set to 1 or cleared to 0)N: value written was negativeZ: value written was zeroP: value written was positiveAffected each time any register is writtenCondition codes are read by conditional branch instructions8Addressing Modes - 1Where is the operand?The addressing modes provide multiple mechanisms for the instruction to specify the location of an operand.Effective Address (EA) The address that is used to locate the operand.LC-2 supports five addressing modes:explicitly in the instruction itself (immediate)in a register in memory, by specifying the address of the operand (two modes: direct and base+offset)the address of a location that contains the address of the operand (indirect)9Immediate & Register OperandsImmediateIf bit 5 = 1, the value in [4:0] (“immediate”) is sign extended (SEXT) to 16 bits and added to the contents of the source register SR1 ([8:6]). Registerif bit 5 = 0, the contents of source register SR2 ([2:0]) are added to the contents of source register SR1 ([8:6]).In both cases, the result goes to the destination register DR ([11:9]). opcodeoperandsADDDRSR11imm[15:12][11:9][8:6][5][4:0]ADDDRSR10[15:12][11:9][8:6][5][2:0]SR2opcodeoperands10Memory Addressing ModesDirect addressingeffective address = [instruction page no.]@[page offset]note that the 9 bit page offset (=> 512 locations) is concatenated with (not added to) the 7 bit page number (=> 128 pages) operand location must be on the same page as current instructionIndirect addressingSame mechanism as above, but the calculated memory location now contains the address of the operand, (i.e. the ea is indirect).Note that the memory has to be accessed twice to get the actual operand.LDDRpage offset[15:12][11:9][8:0]LDIDRpage offset[15:12][11:9][8:0]11Memory Addressing Modes - 2Base+Offset addressingeffective address = (BaseRegister) + offsetzero extend (ZEXT) the 6 bit offset ([5:0]) to 16 bitsadd it to the contents of the Base Register ([8:6])differences from Direct addressing (pageoffset):base offset is added, page offset is concatenatedbase offset range is only 6 bits (=> 64 locations), page offset is 9 bitsbase offset can address any location in memory, page offset only in current pageLDRDRBaseR[15:12][11:9][8:6][5:0]offset12Operate Instructions - 1Arithmetic and Logicarithmetic: add, subtract, multiply, divide (the LC-2 only has add)logic: and, or, not, xor (the LC-2 only has and, not)LC-2: ADD, AND & NOT0 0 0 10 1 10 1 0 0 1 0 1 0 0 ADDR3R2dest regsrc regsrc regR5NOTR3R2dest regsrc reg1 0 0 10 1 10 1 0 0 0 0 0 0 0 13Operate Instructions - 2Notuses one source [8:6] register and one destination [11:9] registerbits [5:0] are all 1s.ADD & ANDdestination register in [11:9], one source register in [8:6]other sourceregister operand: if bit [5] = 0, bits [2:0] specify a register for the other sourceimmediate operand: if bit [5] = 1, bits [4:0] specify the other source number directly, as a 5 bit 2’s complement integer, which is sign extended (SEXT) to 16 bits.14ADD: Two's complement 16-bit AdditionAssembler Instruction ADD DR, SR1, SR2 ; DR = SR1 + SR2 (register addressing) ADD DR, SR1, imm5 ; DR = SR1 + Sext(imm5) (immediate addressing)Encoding 0001 DR SR1 0 00 SR2 0001 DR SR1 1 imm5Examples ADD R2,R3,R6 ADD R2,R3,#1Note: Condition codes are set15AND: Bitwise Logical ANDAssembler Instruction AND DR,SR1,SR2 ; DR = SR1 AND SR2 AND DR,SR1,imm5 ; DR = SR1 AND Sext(imm5) Encoding 0101 DR SR1 0 00 SR2 0101 DR SR1 1 imm5 Examples AND R2,R3,R6 AND R2,R2,#0 ; Clear R2 to 0Note: Condition codes are set.16NOT: Bitwise Logical NOTAssembler Inst. NOT DR,SR ; DR = NOT SREncoding 1001 DR SR 111111Example NOT R2,R6 Note: Condition codes are set.17Data Movement Instructions - 1Move Datafrom CPU register to memory => storenominated register is Sourcefrom memory to register => loadnominated register is Destinationalso to/from I/O devices (later)LC-2 Load/Store InstructionsLD, LDI, LDR, LEA, ST, STI, STRFormat:15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 opcodeDR or SRoperand specifier18Data Movement Instructions - 2LC-2 Load/Store Instructionsimmediate: LEA No Effective Address (EA) calculation; the value (PC[15:9] concatenated with instruction[8:0]) is loaded directly into DR - i.e. DR <= PC[15:9] @ Inst[8:0] direct: LD & ST The EA is [15:9] from PC, [8:0] from instruction (page-offset mode)- i.e. EA = PC[15:9] @ Inst[8:0] DR <= Mem[PC[15:9] @ Inst[8:0] ]indirect: LDI & SDI EA = Mem[ PC[15:9] @ Inst[8:0] ] DR <= Mem[Mem[ PC[15:9] @ Inst[8:0] ]base+offset: LDR & STR (BaseReg is specified by Inst [8:6]) EA = BaseReg + Zext(Inst[5:0]) DR <= Mem[BaseReg + ZEXT(Inst[5:0])]19LD: Load DirectAssembler Inst. LD DR, LABEL ; DR = Mem[LABEL] Encoding 0010 DR page-offset9 Examples LD R2, param Notes: The LABEL must be on the same memory page as the instruction. Condition codes are set.20LDI: Load IndirectAssembler Inst. LDI DR, LABEL ; DR = Mem[Mem[LABEL]] Encoding 1010 DR pgoffset9Examples LDI R2, POINTER Notes: The LABEL must be on the same memory page as the instruction. Condition codes are set.21 LDR: Load Base+IndexAssembler Inst. LDR DR,BaseR,idx6 ; DR = Mem[BaseR+ZEXT(idx6)] Encoding 0110 DR BaseR index6Examples LD R2,R3,#15 ; R2 = Mem[R3+15]Notes: The index is zero-extended to 16 bits. Condition codes are set.22LEA: Load Effective AddressAssembler Inst. LEA DR, LABEL ; DR = LABEL Encoding 1110 DR pgoffset9 (i.e. address of LABEL = PC[15:9] + pgoffset9) Examples LEA R2, DATA ; R2 gets the address of DATA Notes: The LABEL must be on the same memory page as the instruction. Condition codes are set.23 ST: Store DirectAssembler Inst. ST SR, LABEL ; Mem[LABEL] = SREncoding 0011 SR pgoffset9Examples ST R2, VALUE ; Mem[VALUE] = R2 Notes: The LABEL must be on the same memory page as the instruction. Condition codes are not set.24 STI: Store IndirectAssembler Inst. STI SR, LABEL ; Mem[Mem[LABEL]] = SR Encoding 0011 SR pgoffset9 Examples STI R2, POINTER ; Mem[Mem[POINTER]] = R2Notes: The LABEL must be on the same memory page as the instruction. Condition codes are not set. 25STR: Store Base+IndexAssembler Inst. STR SR, BaseR,idx6 ; Mem[BaseR+ZEXT(idx6)]=SREncoding 0111 SR pgoffset9 Examples STR R2, R4, #15 ; Mem[R4+15] = R2 Notes: The index is zero-extended to 16 bits. Condition codes are not set.26Addressing Examples What is the EA for the following instructions?Given:PC = x2081, R6 = x2035, LOC = x2044, Mem[LOC] = x3456ADD R1,R3,R2Register addressing:DR = R1, SR1 = R3, SR2 = R2DR <= ?ADD R5,R1,#15Immediate addressing:DR = R5, SR1 = R1, S2 = 15DR <= ?LD R1,LOCDirect addressing: DR <= ?LDI R2,LOCIndirect addressing: EA = Mem[x2044] = x3456LDR R1,R6,#12Base+Offset addressing:EA = R6+12 = x2035 + x000C = x204127Control InstructionsChange the Program CounterConditionally or notRemember where it was (subroutine calls)LC-2 InstructionsBRx, JMP/JSR, JMPR/JSRR, RET, TRAPBRx, JMP, JSR use direct addressingJMPR, JSRR use base+offset addressingConditional Branch: BRx15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0page offsetNZP28 BR: Conditional Branch Assembler Inst. BR LABEL BRn LABEL BRz LABEL BRp LABEL BRnz LABEL BRnp LABEL BRzp LABEL BRnzp LABELEncoding 0000 n z p pgoffset9Examples BRzp LOOP ; branch to LOOP if previous op returned zero or positive.Note: Branch to LABEL iff the selected condition code(s) is set29TRAP InstructionUsed to invoke an operating system service callTrap vectors: a list of locations of the service call routinesTRAP has one operand which indexes into the trap vector; PC is set to the value (starting point of service routine)Some special trap vectors: * x23: input a character from the keyboard * x21: output a character to the monitor * x25: halt the programMore details later30TRAP: Invoke a system routine Assembler Inst. TRAP trapvecEncoding 1111 0000 trapvect8Examples TRAP x23Note: R7 <= PC (for eventual return) PC <= mem[Zext(trapvect8)]31Data Path - 1Global Bus16-bitconnects all componentsis shared by allMemoryMemory Address Register: MARaddress of location to be accessedMemory Data Register: MDRdata loaded or to be stored32Data Path - 2ALU & RegistersTwo ALU sourcessource 1: registersource 2: register or instructionResult: goes onto bus, then to DRPC & PCMUXPC sends address to MAR for instruction fetchPCMUX: a 4:1 mux that selects the new PCincremented PCBRTRAP, RET or JSR (later)33Data Path - 3MARMUXA 3:1 mux that selects the source of MARRight input: direct, indirect addressingMiddle input: base+offset addressingLeft input: trap instruction34Instruction Cycle - 1Given: PC = x3456, Mem[x3456] = x6684Fetch MAR  PC, PC PC+1 MDR  x6684 IR  MDR Decode Control logic processes the instruction: 0110 011 010 000100 : LDR R3 R2 4Evaluate Address MAR  R2 + 435Instruction Cycle - 2Operand Fetch MDR  value from memory Execute: none for LDRStore Result R3  MDR36