Phần cứng - Chapter 8: Input / Output

Chapter 8Input/Output Basic organization Keyboard input Monitor output Interrupts DMAI/O BasicsDefinitionsInputtransfer data from the outside world to the computer: keyboard, mouse, scanner, bar-code reader, etc.Outputtransfer data from the computer to the outside: monitor, printer, LED display, etc.Peripheral: any I/O device, including disks.LC-2 supports a keyboard and a monitor2Device RegistersI/O InterfaceThrough a set of Device Registers:Status register (device is busy/idle/error)Data register (data to be moved to/from device)The device registers can be read/written by the CPULC-2KBDR: keyboard data registerKBSR: keyboard status registerCRTDR: monitor data registerCRTST: monitor status registerKBSR[15] - keyboard ready (new character available)KBDR[7:0] - character typed (ASCII)CTRSR[15] - CRT readyCTRDR[7:0] - character to be displayed (ASCII)KBSRKBDRCTRSRCTRDRLC-23Addressing Device RegistersSpecial I/O InstructionsRead or write a device register using specialized I/O instructions.Memory Mapped I/OUse existing data movement instructions (Load & Store).Map each device register to a memory address (fixed).CPU communicates with the device registers as if they were memory locations.LC-2Uses memory mapped I/OCRTSRCRTDRKBDRKBSRxF3FCxF3FFxF401xF400LC-2 memory map4Synchronizing CPU and I/OProblemSpeed mismatch between CPU and I/O:CPU runs at > 2 GHz, all I/O is much slower.Example : Keyboard input is at irregular intervals.Need a protocol to keep CPU & KBD synchronizedHandshake synchronizationCPU checks the KBD Ready status bit.If set, CPU reads the data register and resets the Ready bit.Start over.Make CPU-I/O interaction seem to be synchronous5Polling v/s Interrupts (Who’s driving?)Polling - CPU drivingCPU checks the ready bit of status register (as per program instructions).If (KBSR[15] == 1) then load KBDR[7:0] to a register.If the I/O device is very slow, CPU is busy waiting.Interrupt - I/O drivingEvent triggered - when the I/O device is ready, it sets a flag: the interrupt signal.When interrupt is set, the CPU is forced to an interrupt service routine (ISR) which services the interrupting device.There are different priority levels of interrupt. Specialized instructions can mask an interrupt level.6Polling AlgorithmAlgorithmInputThe CPU loops checking the Ready bitWhen bit is set, a character is availableCPU loads the character OutputCPU loops checking the Ready bitWhen bit is set, monitor is ready for next characterCPU stores a character in monitor data registerDetails (Keyboard)When key is struckASCII code of character goes into KBDR[7:0]KBSR[15] (Ready Bit) is set to 1Keyboard is locked until CPU reads KBDRThen Ready Bit is cleared, keyboard is unlocked7Polling RoutinesSTART LDI R1, A ;Loop if Ready not set BRzp START LDI R0,B ;If set, load char BR NEXT_TASK A .FILL xF400 ;Address of KBSR B .FILL xF401 ;Address of KBDRInput a character from keyboardSTART LDI R1, A ;Loop if Ready not set BRzp START STI R0,B ;If set, send char BR NEXT_TASK A .FILL xF3FC ;Address of CRTSR B .FILL xF3FF ;Address of CRTDROutput a character to the monitor8Keyboard Echo: combine the aboveSTART LDI R1,KBSR ;Loop if KB not ready BRzp START LDI R0,KBDR ;Get characterECHO LDI R1,CRTSR ;Loop if MON not ready BRzp ECHO STI R0,CRTDR ;Send character BR NEXT_TASKKBSR .FILL xF3FC ;Address of KBSRKBDR .FILL xF3FF ;Address of KBDRCRTSR .FILL xF400 ;Address of CRTSRCRTDR .FILL xF401 ;Address of CRTDR9Example: Print a string LEA R1,STR ;Load address of string LOOP LDR R0,R1,#0 ;get next char to R0 BRZ DONE ;string ends with 0 L2 LDI R3,CRTSR ;Loop until MON is ready BRzp L2 STI R0,CRTDR ;Write next character ADD R1,R1,#1 ; Set address to next char BR LOOP STR .STRINGZ "Char String"DONE HALT10Interrupts - MoreInterrupt mask register: each bit specifies whether the corresponding device is allowed to interrupt.In the CPU, the control logic checks the INT bit before each instruction fetch stage.If INT is set:(PC) is savedPC  address of corresponding ISRChange mask settings (allow nested interrupts)ISR is executedReset mask settingsSaved PC is restoredHow can CPU tell who interrupted?Interrupt mask registerInterrupt linesCPU INT11Interrupt – Who called?How can CPU tell who interrupted?PollingVectored InterruptsMultiple CPU INT lines, each dedicated to a device or group of devices (Intel: INT0, INT1 )Each INT line sends the CPU to a specific ISR (Interrupt Service Routine).The ISR must figure out who called if more than one device is associated with that INT line.Daisy ChainCPU sends an interrupt acknowledge (IACK) that is passed from one device to another.Interrupting device puts the address of its ISR on the Data Bus.Order of devices in the chain is the priority.Example: SCSIIData busIACK12DMA – Direct Memory AccessDMAA device specialized in transferring data between memory and an I/O device (disk).CPU writes the starting address and size of the region of memory to be copied, both source and destination addresses.DMA does the transfer in the background.It accesses the memory only when the CPU is not accessing it (cycle stealing).I/O DevCPUmemoryDMA13