Single-Phase Multifunction Metering IC with di/dt Sensor Interface

The contents of the offset correction registers are 6-bit, sign and magnitude coded. The weight of the LSB depends on the gain setting, i.e., 1, 2, 4, 8, or 16. Table 6 shows the correctable offset span for each of the gain settings and the LSB weight (mV) for the offset correction registers. The maximum value that can be written to the offset correction registers is ±31d—see Figure 34. Figure 34 shows the relationship between the offset correction register contents and the offset (mV) on the analog inputs for a gain setting of 1. In order to perform an offset adjustment, the analog inputs should be first connected to AGND, and there should be no signal on either Channel 1 or Channel 2. A read from Channel 1 or Channel 2 using the waveform register indicates the offset in the channel. This offset can be canceled by writing an equal and opposite offset value to the Channel 1 offset register, or an equal value to the Channel 2 offset register. The offset correction can be confirmed by performing another read. Note when adjusting the offset of Channel 1, one should disable the digital integrator and the HPF

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RESET THE INTERRUPT STATUS READ REGISTER ADDR. 0x0C INTERRUPT? NO NO YES YES 02875-A-007 RESET THE INTERRUPT STATUS READ REGISTER ADDR. 0x0C INTERRUPT? Figure 81. Calibrating Watt Gain Using an Accurate Source Equation 47 describes the relationship between the expected LAENERGY value and the LAENERGY measured in the test condition: WGAIN = INT ⎟⎟⎠ ⎞ ⎜⎜⎝ ⎛ ×⎟⎟⎠ ⎞ ⎜⎜⎝ ⎛ − 12 )( )( 21 nominalIB expectedIB LAENERGY LAENERGY (47) The nominal LAENERGY reading, LAENERGYIB(nominal), is the LAENERGY reading with the test current applied. The expected LAENERGY reading is calculated from the following equation: LAENERGYIB(expected) = INT ⎟⎟ ⎟⎟ ⎠ ⎞ ⎜⎜ ⎜⎜ ⎝ ⎛ ×+ + × WDIV CFDEN CFNUM TimeonAccumulatiCF expectedIB 1 1 (s))( (48) where CFIB(expected)(Hz) is calculated from Equation 34, accumula- tion time is calculated from Equation 37, and the line period is determined from the PERIOD register according to Equation 38. For this example: Meter Constant: MeterConstant(imp/Wh) = 3.2 Test Current: Ib = 10 A Line Voltage: Vnominal = 220 V Line Frequency: fl = 50 Hz Half Line Cycles: LINECYCIB = 2000 CF Numerator: CFNUM = 0 CF Denominator: CFDEN = 489 Energy Reading at Base Current: LAENERGYIB (nominal) = 17174 Period Register Reading: PERIOD = 8959 Clock Frequency: CLKIN = 3.579545 MHz CFexpected is calculated to be 1.9556 Hz according to Equation 34. LAENERGYexpected is calculated to be 19186 using Equation 48. CFIB(expected)(Hz) = )(cos( s/h3600 A10V220imp/Wh200.3 ϕ××× = 1.9556 Hz LAENERGYIB(expected) = INT ⎟⎟ ⎟⎟ ⎠ ⎞ ⎜⎜ ⎜⎜ ⎝ ⎛ ×+ + ××× WDIV CFDEN CFNUM CLKINPERIODLINECYCCF IBexpectedIB 1 1 /82/)( LAENERGYIB(expected) = INT 1 1489 1 )10579545.3/(889592/20009556.1 6 ⎟⎟ ⎟⎟ ⎠ ⎞ ⎜⎜ ⎜⎜ ⎝ ⎛ + ×××× = 19186)4.19186( =INT WGAIN is calculated to be 480 using Equation 47. WGAIN = INT 48021 17174 19186 12 =⎟⎠ ⎞⎜⎝ ⎛ ×⎟⎠ ⎞⎜⎝ ⎛ − Note that WGAIN is a signed twos complement register. With WDIV and CFNUM set to 0, LAENERGY can be expressed as ADE7753 Rev. C | Page 42 of 60 LAENERGYIB(expected) = ))1(/82/( )( +×××× CFDENCLKINPERIODLINECYCCFINT IBexpectedIB The calculated Wh/LSB ratio for the active energy register, using Equation 39 is 6.378 × 10−4: 410378.6 imp/Wh200.3 )1489( 1 LSB Wh −×=+= Watt Offset Offset calibration allows outstanding performance over a wide dynamic range, for example, 1000:1. To do this calibration two measurements are needed at unity power factor, one at Ib and the other at the lowest current to be corrected. Either calibration frequency or line cycle accumulation measurements can be used to determine the energy offset. Gain calibration should be performed prior to offset calibration. Offset calibration is performed by determining the active energy error rate. Once the active energy error rate has been determined, the value to write to the APOS register to correct the offset is calculated. APOS = − CLKIN RateErrorAENERGY 352× (49) The AENERGY registers update at a rate of CLKIN/4. The twos complement APOS register provides a fine adjustment to the active power calculation. It represents a fixed amount of power offset to be adjusted every CLKIN/4. The 8 LSBs of the APOS register are fractional such that one LSB of APOS represents 1/256 of the least significant bit of the internal active energy register. Therefore, one LSB of the APOS register represents 2−33 of the AENERGY[23:0] active energy register. The steps involved in determining the active energy error rate for both line accumulation and reference meter calibration options are shown in the following sections. Calibrating Watt Offset Using a Reference Meter Example Figure 82 shows the steps involved in calibrating watt offset with a reference meter. WRITE APOS VALUE TO THE APOS REGISTER: ADDR. 0x11 MEASURE THE % ERROR BETWEEN THE CF OUTPUT AND THE REFERENCE METER OUTPUT, AND THE LOAD IN WATTS SET ITEST = IMIN, VTEST = VNOM, PF = 1 02875-A-008 CALCULATE APOS. SEE EQUATION 49. Figure 82. Calibrating Watt Offset Using a Reference Meter For this example: Meter Constant: MeterConstant(imp/Wh) = 3.2 Minimum Current: IMIN = 40 mA Load at Minimum Current: WIMIN = 9.6 W CF Error at Minimum Current: %ERRORCF(IMIN) = 1.3% CF Numerator: CFNUM = 0 CF Denominator: CFDEN = 489 Clock Frequency: CLKIN = 3.579545 MHz Using Equation 49, APOS is calculated to be −522 for this example. CF Absolute Error = CFIMIN(nominal) − CFIMIN(expected) (50) CF Absolute Error = (%ERRORCF(IMIN)) × WIMIN × 3600 (imp/Wh)antMeterConst (51) CF Absolute Error = Hz000110933.0 3600 200.36.9 100 %3.1 =××⎟⎠ ⎞⎜⎝ ⎛ Then, AENERGY Error Rate (LSB/s) = CF Absolute Error × 1 1 + + CFNUM CFDEN (52) AENERGY Error Rate (LSB/s) = 0.000110933 × 05436.0 1 490 = Using Equation 49, APOS is −522. APOS = − 522 10579545.3 205436.0 6 35 −=× × APOS can be represented as follows with CFNUM and WDIV set at 0: APOS = − CLKIN CFDEN antMeterConst WERROR IMINIMINCF 35 )( 2)1(3600 (imp/Wh) )(% ×+××× ADE7753 Rev. C | Page 43 of 60 Calibrating Watt Offset with an Accurate Source Example Figure 83 is the flowchart for watt offset calibration with an accurate source. SET HALF LINE CYCLES FOR ACCUMULATION IN LINECYC REGISTER ADDR. 0x1C SET ITEST = IMIN, VTEST = VNOM, PF = 1 CALCULATE APOS. SEE EQUATION 49. SET MODE FOR LINE CYCLE ACCUMULATION ADDR. 0x09 = 0x0080 ENABLE LINE CYCLE ACCUMULATION INTERRUPT ADDR. 0x0A = 0x04 READ LINE ACCUMULATION ENERGY ADDR. 0x04 RESET THE INTERRUPT STATUS READ REGISTER ADDR. 0x0C INTERRUPT? NO NO YES YES RESET THE INTERRUPT STATUS READ REGISTER ADDR. 0x0C INTERRUPT? WRITE APOS VALUE TO THE APOS REGISTER: ADDR. 0x11 02875-A-009 Figure 83. Calibrating Watt Offset with an Accurate Source For this example: Meter Constant: MeterConstant(imp/Wh) = 3.2 Line Voltage: Vnominal = 220 V Line Frequency: fl = 50 Hz CF Numerator: CFNUM = 0 CF Denominator: CFDEN = 489 Base Current: Ib = 10 A Half Line Cycles Used at Base Current: LINECYC(IB) = 2000 Period Register Reading: PERIOD = 8959 Clock Frequency: CLKIN = 3.579545 MHz Expected LAENERGY Register Value at Base Current (from the Watt Gain section):LAENERGYIB(expected) = 19186 Minimum Current: IMIN = 40 mA Number of Half Line Cycles used at Minimum Current: LINECYC(IMIN) = 35700 Active energy Reading at Minimum Current: LAENERGYIMIN(nominal) = 1395 The LAENERGYexpected at IMIN is 1370 using Equation 53. LAENERGYIMIN(expected) = INT ⎟⎟⎠ ⎞ ⎜⎜⎝ ⎛ ×× IB MIN expectedIB B MIN LINECYC LINECYCI LAENERGY I I )( (53) LAENERGYIMIN(expected) = INT 1370)80.1369( 2000 3570019186 10 04.0 ==⎟⎠ ⎞⎜⎝ ⎛ ×× INT where: LAENERGYIB(expected) is the expected LAENERGY reading at Ib from the watt gain calibration. LINECYCIMIN is the number of half line cycles that energy is accumulated over when measuring at IMIN. More line cycles could be required at the minimum current to minimize the effect of quantization error on the offset calibration. For example, if a test current of 40 mA results in an active energy accumulation of 113 after 2000 half line cycles, one LSB variation in this reading represents an 0.8% error. This measurement does not provide enough resolution to calibrate out a <1% offset error. However, if the active energy is accumulated over 37,500 half line cycles, one LSB variation results in 0.05% error, reducing the quantization error. APOS is −672 using Equations 55 and 49. LAENERGY Absolute Error = LAENERGYIMIN(nominal) − LAENERGYIMIN(expected) LAENERGY Absolute Error = 1395 − 1370 = 25 (54) AENERGY Error Rate (LSB/s) = PERIOD CLKIN LINECYC ErrorAbsoluteLAENERGY ×× 82/ (55) AENERGY Error Rate (LSB/s) = 069948771.0 89598 10579545.3 2/35700 25 6 =× ×× APOS = − CLKIN RateErrorAENERGY 352× APOS = − 672 10579545.3 2069948771.0 6 35 −=× × ADE7753 Rev. C | Page 44 of 60 Phase Calibration The PHCAL register is provided to remove small phase errors. The ADE7753 compensates for phase error by inserting a small time delay or advance on the voltage channel input. Phase leads up to 1.84° and phase lags up to 0.72° at 50 Hz can be corrected. The error is determined by measuring the active energy at IB and two power factors, PF = 1 and PF =0.5 inductive. Some CTs may introduce large phase errors that are beyond the range of the phase calibration register. In this case, coarse phase compensation has to be done externally with an analog filter. The phase error can be obtained from either CF or LAENERGY measurements: Error = 2 2 )( )(5., expectedIB expectedIBPFIB LAENERGY LAENERGYLAENERGY −= (56) If watt gain and offset calibration have been performed, there should be 0% error in CF at unity power factor and then: Error = %ERRORCF(IB,PF = .5) /100 (57) The phase error is Phase Error (°) = −Arcsin ⎟⎟⎠ ⎞⎜⎜⎝ ⎛ 3 Error (58) The relationship between phase error and the PHCAL phase correction register is PHCAL= INT ( ) +⎟⎠ ⎞⎜⎝ ⎛ °×° 360 PERIODErrorPhase 0x0D (59) The expression for PHCAL can be simplified using the assumption that at small x: Arcsin(x) ≈ x The delay introduced in the voltage channel by PHCAL is Delay = (PHCAL − 0x0D) × 8/CLKIN (60) The delay associated with the PHCAL register is a time delay if (PHCAL − 0x0D) is positive but represents a time advance if this quantity is negative. There is no time delay if PHCAL = 0x0D. The phase correction is in the opposite direction of the phase error. Phase Correction (°) = −(PHCAL − 0x0D) PERIOD °× 360 (61) Calibrating Phase Using a Reference Meter Example A power factor of 0.5 inductive can be assumed if the pulse output rate of the reference meter is half of its PF = 1 rate. Then the %ERROR between CF and the pulse output of the reference meter can be used to perform the preceding calculations. WRITE PHCAL VALUE TO THE PHCAL REGISTER: ADDR. 0x10 MEASURE THE % ERROR BETWEEN THE CF OUTPUT AND THE REFERENCE METER OUTPUT SET ITEST = Ib, VTEST = VNOM, PF = 0.5 02875-A-010 CALCULATE PHCAL. SEE EQUATION 59. Figure 84. Calibrating Phase Using a Reference Meter For this example: CF % Error at PF = .5 Inductive: %ERRORCF(IB,PF = .5) = 0.215% PERIOD Register Reading: PERIOD = 8959 Then PHCAL is 11 using Equations 57 through 59: Error = 0.215% / 100 = 0.00215 Phase Error (°) = −Arcsin °−=⎟⎟⎠ ⎞⎜⎜⎝ ⎛ 07.0 3 00215.0 PHCAL = INT ⎟⎠ ⎞⎜⎝ ⎛ °×°− 360 895907.0 +0x0D = −2 + 13 = 11 PHCAL can be expressed as follows: PHCAL = INT ⎟⎟⎠ ⎞ ⎜⎜⎝ ⎛ π×⎟⎟⎠ ⎞⎜⎜⎝ ⎛− 23 Arcsin PERIODError + 0x0D (62) Note that PHCAL is a signed twos complement register. Setting the PHCAL register to 11 provides a phase correction of 0.08° to correct the phase lead: Phase Correction (°) = PERIOD PHCAL °×−− 360)0x0D( Phase Correction (°) = °=°×−− 08.0 8960 360)0x0D11( ADE7753 Rev. C | Page 45 of 60 Calibrating Phase with an Accurate Source Example With an accurate source, line cycle accumulation is a good method of calibrating phase error. The value of LAENERGY must be obtained at two power factors, PF = 1 and PF = 0.5 inductive. SET HALF LINE CYCLES FOR ACCUMULATION IN LINECYC REGISTER ADDR. 0x1C SET ITEST = Ib, VTEST = VNOM, PF = 0.5 CALCULATE PHCAL. SEE EQUATION 59. SET MODE FOR LINE CYCLE ACCUMULATION ADDR. 0x09 = 0x0080 ENABLE LINE CYCLE ACCUMULATION INTERRUPT ADDR. 0x0A = 0x04 READ LINE ACCUMULATION ENERGY ADDR. 0x04 RESET THE INTERRUPT STATUS READ REGISTER ADDR. 0x0C INTERRUPT? NO NO YES YES RESET THE INTERRUPT STATUS READ REGISTER ADDR. 0x0C INTERRUPT? WRITE PHCAL VALUE TO THE PHCAL REGISTER: ADDR. 0x10 02875-A-011 Figure 85. Calibrating Phase with an Accurate Source For this example: Meter Constant: MeterConstant(imp/Wh) = 3.2 Line Voltage: Vnominal = 220 V Line Frequency: fl = 50 Hz CF Numerator: CFNUM = 0 CF Denominator: CFDEN = 489 Base Current: Ib = 10 A Half Line Cycles Used at Base Current: LINECYCIB = 2000 PERIOD Register: PERIOD = 8959 Expected Line Accumulation at Unity Power Factor (from Watt Gain Section: LAENERGYIB(expected) = 19186 Active Energy Reading at PF = .5 inductive: LAENERGYIB, PF = .5 = 9613 The error using Equation 56 is Error = 0021.0 2 19186 2 191869613 = − Phase Error (°) = −Arcsin °−=⎟⎟⎠ ⎞⎜⎜⎝ ⎛ 07.0 3 0021.0 Using Equation 59, PHCAL is calculated to be 11. PHCAL = INT 111320x0D 360 895907.0 =+−=+⎟⎠ ⎞⎜⎝ ⎛ °×°− Note that PHCAL is a signed twos complement register. The phase lead is corrected by 0.08° when the PHCAL register is set to 11: Phase Correction (°) = PERIOD PHCAL °×−− 360)0x0D( Phase Correction (°) = °=°×−− 08.0 8960 360)0x0D11( VRMS and IRMS Calibration VRMS and IRMS are calculated by squaring the input in a digital multiplier. )2cos()sin(V2)sin(V2)( tVVtttv 222 ω×−=ω×ω= (63) The square of the rms value is extracted from v2(t) by a low-pass filter. The square root of the output of this low-pass filter gives the rms value. An offset correction is provided to cancel noise and offset contributions from the input. There is ripple noise from the 2ω term because the low-pass filter does not completely attenuate the signal. This noise can be minimized by synchronizing the rms register readings with the zero crossing of the voltage signal. The IRQ output can be configured to indicate the zero crossing of the voltage signal. This flowchart demonstrates how VRMS and IRMS readings are synchronized to the zero crossings of the voltage input. SET INTERRUPT ENABLE FOR ZERO CROSSING ADDR. 0x0A = 0x0010 RESET THE INTERRUPT STATUS READ REGISTER ADDR. 0x0C INTERRUPT? NO YES 02875-A-003 READ VRMS OR IRMS ADDR. 0x17; 0x16 RESET THE INTERRUPT STATUS READ REGISTER ADDR. 0x0C Figure 86. Synchronizing VRMS and IRMS Readings with Zero Crossings ADE7753 Rev. C | Page 46 of 60 Apparent Energy Voltage rms compensation is done after the LPF3 filter (see Figure 56). Apparent energy gain calibration is provided for both meter-to- meter gain adjustment and for setting the VAh/LSB constant. VRMS = VRMS0 + VRMSOS (64) VAENERGY = ⎟⎠ ⎞⎜⎝ ⎛ +×× 1221 1 VAGAIN VADIV VAENERGYinitial (68) where: VRMS0 is the rms measurement without offset correction. VRMS is linear from full-scale to full-scale/20. VADIV is similar to the CFDEN for the watt hour calibration. It should be the same across all meters and determines the VAh/LSB constant. VAGAIN is used to calibrate individual meters. To calibrate the offset, two VRMS measurements are required, for example, at Vnominal and Vnominal/10. Vnominal is set at half of the full-scale analog input range so the smallest linear VRMS reading is at Vnominal/10. VRMSOS = 12 1221 VV VRMSVVRMSV − ×−× (65) Apparent energy gain calibration should be performed before rms offset correction to make most efficient use of the current test points. Apparent energy gain and watt gain compensation require testing at Ib while rms and watt offset correction require a lower test current. Apparent energy gain calibration can be done at the same time as the watt-hour gain calibration using line cycle accumulation. In this case, LAENERGY and LVAENERGY, the line cycle accumulation apparent energy register, are both read following the line cycle accumulation interrupt. Figure 87 shows a flowchart for calibrating active and apparent energy simultaneously. where VRMS1 and VRMS2 are rms register values without offset correction for input V1 and V2, respectively. If the range of the 12-bit, twos complement VRMSOS register is not enough, the voltage channel offset register, CH2OS, can be used to correct the VRMS offset. Current rms compensation is performed before the square root: IRMS2 = IRMS02 + 32768 × IRMSOS (66) VAGAIN = INT ⎟⎟⎠ ⎞ ⎜⎜⎝ ⎛ ×⎟⎟⎠ ⎞ ⎜⎜⎝ ⎛ − 12 )( )( 21 nominalIB expectedIB LVAENERGY LVAENERGY (69) where IRMS0 is the rms measurement without offset correction. The current rms calculation is linear from full-scale to full- scale/100. LVAENERGYIB(expected) = INT ⎟⎟ ⎟⎟ ⎠ ⎞ ⎜⎜ ⎜⎜ ⎝ ⎛ × × × (s) s/h3600 timeonAccumulati constant LSB VAh IV Bnominal (70) To calibrate this offset, two IRMS measurements are required, for example, at Ib and IMAX/50. IMAX is set at half of the full-scale analog input range so the smallest linear IRMS reading is at IMAX/50. IRMSOS = 2 1 2 2 2 1 2 2 2 2 2 1 II IRMSIIRMSI − ×−×× 32768 1 (67) The accumulation time is determined from Equation 37 and the line period can be determined from the PERIOD register accord- ing to Equation 38. The VAh represented by the VAENERGY register is where IRMS1 and IRMS2 are rms register values without offset correction for input I1 and I2, respectively. VAh = VAENERGY × VAh/LSB constant (71) The VAh/LSB constant can be verified using this equation: LVAENERGY timeonAccumulatiVA constantLSB VAh 3600 (s)×= (72) ADE7753 Rev. C | Page 47 of 60 CALCULATE CFDEN VALUE FOR DESIGN WRITE CFDEN VALUE TO CFDEN REGISTER ADDR. 0x15 = CFDEN SET HALF LINE CYCLES FOR ACCUMULATION IN LINECYC REGISTER ADDR. 0x1C SET ITEST = Ib, VTEST = VNOM, PF = 1 CALCULATE WGAIN. SEE EQUATION 47. SET MODE FOR LINE CYCLE ACCUMULATION ADDR. 0x09 = 0x0080 ENABLE LINE CYCLE ACCUMULATION INTERRUPT ADDR. 0x0A = 0x04 READ LINE ACCUMULATION ENERGY ACTIVE ENERGY: ADDR. 0x04 APPARAENT ENERGY: ADDR. 0x07 RESET THE INTERRUPT STATUS READ REGISTER ADDR. = 0x0C INTERRUPT? NO NO YES YES 02875-A-004 RESET THE INTERRUPT STATUS READ REGISTER ADDR. = 0x0C INTERRUPT? WRITE WGAIN VALUE TO ADDR. 0x12 CALCULATE VAGAIN. SEE EQUATION 69. WRITE VGAIN VALUE TO ADDR. 0x1A Figure 87. Active/Apparent Gain Calibration Reactive Energy Reactive energy is only available in line accumulation mode in the ADE7753. The accumulated reactive energy over LINECYC number of half line cycles is stored in the LVARENERGY register. In the ADE7753, a low-pass filter at 2 Hz on the current channel is implemented for the reactive power calculation. This provides the 90 degree phase shift needed to calculate the reactive power. This filter introduces 1/f attenuation in the reactive energy accumulated. Compensation for this attenuation can be done externally in a microcontroller. The microcontroller can use the LVARENERGY register in order to produce a pulse output similar to the CF pulse for reactive energy. To create a VAR pulse, an impulse/VARh constant must be determined. The 1/f attenuation correction factor is determined by comparing the nominal reactive energy accumulation rate to the expected value. The attenuation correction factor is multi- plied by the contents of the LVARENERGY register, with the ADE7753 in line accumulation mode. ADE7753 Rev. C | Page 48 of 60 The impulse/LSB ratio used to convert the value in the LVARENERGY register into a pulse output can be expressed in terms of impulses/VARh and VARh/LSB. imp/LSB = nominal expectedIB VARCF VARCF LSBVARhVARhimp )(// =× (73) VARCFIB(expected) = )sin( s/h3600 )/( ϕ××× bnominal IVVARhimptVARConstan (74) VARCFIB(nominal) = PERIODtimeonAccumulati PERIODLVARENERGYIB × × (s) Hz50 (75) where the accumulation time is calculated from Equation 37. The line period can be determined from the PERIOD register according to Equation 38. Then VAR can be determined from the LVARENERGY register value: VARh = PERIOD PERIODLSBVARhLVARENERGYIB Hz50/ ×× (76) VAR = PERIODtimeonAccumulati PERIODLSBVARhLVARENERGYIB × ×× (s) s/h3600/ Hz50 (77) The PERIOD50 Hz/PERIOD factor in the preceding VAR equations is the correction factor for the 1/f frequency attenuation of the low-pass filter. The PERIOD50 Hz term refers to the line period at calibration and could represent a frequency other than 50 Hz. CLKIN FREQUENCY In this data sheet, the characteristics of the ADE7753 are shown when CLKIN frequency is equal to 3.579545 MHz. However, the ADE7753 is designed to have the same accuracy at any CLKIN frequency within the specified range. If the CLKIN frequency is not 3.579545 MHz, various timing and filter characteristics need to be redefined with the new CLKIN frequency. For example, the cutoff frequencies of all digital filters such as LPF1, LPF2, or HPF1, shift in proportion to the change in CLKIN frequency according to the following equation: MHz FrequencyCLKIN FrequencyOriginalFrequencyNew 579545.3 ×= (78) The change of CLKIN frequency does not affect the timing characteristics of the serial interface because the data transfer is synchronized with serial clock signal (SCLK). But one needs to observe the read/write timing of the serial data transfer—see the ADE7753 timing characteristics in Table 2. Table 11 lists various timing changes that are affected by CLKIN frequency. Table 11. Frequency Dependencies of the ADE7753 Parameters Parameter CLKIN Dependency Nyquist Frequency for CH 1 and CH 2 ADCs CLKIN/8 PHCAL Resolution (Seconds per LSB) 4/CLKIN Active Energy Register Update Rate (Hz) CLKIN/4 Waveform Sampling Rate (per Second) WAVSEL 1,0 = 0 0 CLKIN/128 0 1 CLKIN/256 1 0 CLKIN/512 1 1 CLKIN/1024 Maximum ZXTOUT Period 524,288/CLKIN SUSPENDING ADE7753 FUNCTIONALITY The analog and the digital circuit can be suspended separately. The analog portion of the ADE7753 can be suspended by setting the ASUSPEND bit (Bit 4) of the mode register to logic high— see the Mode Register (0x9) section. In suspend mode, all wave- form samples from the ADCs are set to 0. The digital circuitry can be halted by stopping the CLKIN input and maintaining a logic high or low on the CLKIN pin. The ADE7753 can be reactivated by restoring the CLKIN input and setting the ASUSPEND bit to logic low. CHECKSUM REGISTER The ADE7753 has a checksum register (CHECKSUM[5:0]) to ensure the data bits received in the last serial read operation are not corrupted. The 6-bit checksum register is reset before the first bit (MSB of the register to be read) is put on the DOUT pin. During a serial read operation, when each data bit becomes available on the rising edge of SCLK, the bit is added to the checksum register. In the end of the serial read operation, the content of the checksum register is equal to the sum of all ones in the register previously read. Using the checksum register, the user can determine if an error has occurred during the last read operation. Note that a read to the checksum register also generates a checksum of the checksum register itself. CONTENT OF REGISTER (n-bytes) CHECKSUM REGISTER ADDR: 0x3E + + DOUT 02875-0-077 Figure 88. Checksum Register for Serial Interface Read ADE7753 Rev. C | Page 49 of 60 ADE7753 SERIAL INTERFACE All ADE7753 functionality is accessible via several on-chip registers—see Figure 89. The contents of these registers can be updated or read using the on-chip serial interface. After power- on or toggling the RESET pin low or a falling edge on CS, the ADE7753 is placed in communications mode. In communica- tions mode, the ADE7753 expects a write to its communications register. The data written to the communications register determines whether the next data transfer operation is a read or a write and also which register is accessed. Therefore all data transfer operations with the ADE7753, whether a read or a write, must begin with a write to the communications register. COMMUNICATIONS REGISTER IN OUT IN OUT IN OUT IN OUT IN OUT REGISTER 1 REGISTER 2 REGISTER 3 REGISTER n–1 REGISTER n REGISTER ADDRESS DECODE DIN DOUT 02875-0-078 Figure 89. Addressing ADE7753 Registers via the Communications Register The communications register is an 8-bit wide register. The MSB determines whether the next data transfer operation is a read or a write. The six LSBs contain the address of the register to be accessed—see the Communications Register section for a more detailed description. Figure 90 and Figure 91 show the data transfer sequences for a read and write operation, respectively. On completion of a data transfer (read or write), the ADE7753 once again enters communications mode. A data transfer is complete when the LSB of the ADE7753 register being addressed (for a write or a read) is transferred to or from the ADE7753. MULTIBYTE COMMUNICATIONS REGISTER WRITE DIN SCLK CS DOUT READ DATA ADDRESS00 02875-0-079 Figure 90. Reading Data from the ADE7753 via the Serial Interface COMMUNICATIONS REGISTER WRITE DIN SCLK CS ADDRESS01 02875-0-080 MULTIBYTE READ DATA Figure 91. Writing Data to the ADE7753 via the Serial Interface The serial interface of the ADE7753 is made up of four signals: SCLK, DIN, DOUT, and CS. The serial clock for a data transfer is applied at the SCLK logic input. This logic input has a Schmitt-trigger input structure that allows slow rising (and falling) clock edges to be used. All data transfer operations are synchronized to the serial clock. Data is shifted into the ADE7753 at the DIN logic input on the falling edge of SCLK. Data is shifted out of the ADE7753 at the DOUT logic output on a rising edge of SCLK. The CS logic input is the chip-select input. This input is used when multiple devices share the serial bus. A falling edge on CS also resets the serial interface and places the ADE7753 into communications mode. The CS input should be driven low for the entire data transfer operation. Bringing CS high during a data transfer operation aborts the transfer and places the serial bus in a high impedance state. The CS logic input can be tied low if the ADE7753 is the only device on the serial bus. However, with CS tied low, all initiated data transfer operations must be fully completed, i.e., the LSB of each register must be transferred because there is no other way of bringing the ADE7753 back into communications mode without resetting the entire device by using RESET. ADE7753 Rev. C | Page 50 of 60 ADE7753 Serial Write Operation The serial write sequence takes place as follows. With the ADE7753 in communications mode (i.e., the CS input logic low), a write to the communications register first takes place. The MSB of this byte transfer is a 1, indicating that the data transfer operation is a write. The LSBs of this byte contain the address of the register to be written to. The ADE7753 starts shifting in the register data on the next falling edge of SCLK. All remaining bits of register data are shifted in on the falling edge of subsequent SCLK pulses—see . As explained earlier, the data write is initiated by a write to the communications register followed by the data. During a data write operation to the ADE7753, data is transferred to all on-chip registers one byte at a time. After a byte is transferred into the serial port, there is a finite time before it is transferred to one of the ADE7753 on-chip registers. Although another byte transfer to the serial port can start while the previous byte is being transferred to an on-chip register, this second byte transfer Figure 92 should not finish until at least 4 μs after the end of the previous byte transfer. This functionality is expressed in the timing specification t6—see Figure 92. If a write operation is aborted during a byte transfer (CS brought high), then that byte cannot be written to the destination register. Destination registers can be up to 3 bytes wide—see the ADE7753 Register Description tables. Therefore the first byte shifted into the serial port at DIN is transferred to the MSB (most significant byte) of the destination register. If, for example, the addressed register is 12 bits wide, a 2-byte data transfer must take place. The data is always assumed to be right justified, therefore in this case, the four MSBs of the first byte would be ignored and the four LSBs of the first byte written to the ADE7753 would be the four MSBs of the 12-bit word. Figure 93 illustrates this example. DIN SCLK CS t2 t3 t1 t4 t5 t7 t6 t8 COMMAND BYTE MOST SIGNIFICANT BYTE LEAST SIGNIFICANT BYTE 1 0 A4A5 A3 A2 A1 A0 DB7 DB0 DB7 DB0 t7 02875-0-081 Figure 92. Serial Interface Write Timing SCLK DIN X X X X DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 MOST SIGNIFICANT BYTE LEAST SIGNIFICANT BYTE 02875-0-082 Figure 93. 12-Bit Serial Write Operation ADE7753 Rev. C | Page 51 of 60 ADE7753 Serial Read Operation During a data read operation from the ADE7753, data is shifted out at the DOUT logic output on the rising edge of SCLK. As is the case with the data write operation, a data read must be preceded with a write to the communications register. With the ADE7753 in communications mode (i.e., CS logic low), an 8-bit write to the communications register first takes place. The MSB of this byte transfer is a 0, indicating that the next data transfer operation is a read. The LSBs of this byte contain the address of the register that is to be read. The ADE7753 starts shifting out of the register data on the next rising edge of SCLK—see . At this point, the DOUT logic output leaves its high impedance state and starts driving the data bus. All remaining bits of register data are shifted out on subsequent SCLK rising edges. The serial interface also enters communications mode again as soon as the read has been completed. At this point, the DOUT logic output enters a high impedance state on the falling edge of the last SCLK pulse. The read operation can be aborted by bringing the Figure 94 CS logic input high before the data transfer is complete. The DOUT output enters a high impedance state on the rising edge of CS. When an ADE7753 register is addressed for a read operation, the entire contents of that register are transferred to the serial port. This allows the ADE7753 to modify its on-chip registers without the risk of corrupting data during a multibyte transfer. Note that when a read operation follows a write operation, the read command (i.e., write to communications register) should not happen for at least 4 μs after the end of the write operation. If the read command is sent within 4 μs of the write operation, the last byte of the write operation could be lost. This timing constraint is given as timing specification t9. SCLK CS t1 t10 t13 0 0 A4A5 A3 A2 A1 A0 DB0DB7 DB0DB7 DIN DOUT t11 t11 t12 COMMAND BYTE MOST SIGNIFICANT BYTE LEAST SIGNIFICANT BYTE t9 02875-0-083 Figure 94. Serial Interface Read Timing ADE7753 Rev. C | Page 52 of 60 ADE7753 REGISTERS Table 12. Summary of Registers by Address Address Name R/W No. Bits Default Type1 Description 0x01 WAVEFORM R 24 0x0 S Waveform Register. This read-only register contains the sampled waveform data from either Channel 1, Channel 2, or the active power signal. The data source and the length of the waveform registers are selected by data Bits 14 and 13 in the mode register—see the Channel 1 Sampling and Channel 2 Sampling sections. 0x02 AENERGY R 24 0x0 S Active Energy Register. Active power is accumulated (integrated) over time in this 24-bit, read-only register—see the Energy Calculation section. 0x03 RAENERGY R 24 0x0 S Same as the active energy register except that the register is reset to 0 following a read operation. 0x04 LAENERGY R 24 0x0 S Line Accumulation Active Energy Register. The instantaneous active power is accumulated in this read-only register over the LINECYC number of half line cycles. 0x05 VAENERGY R 24 0x0 U Apparent Energy Register. Apparent power is accumulated over time in this read-only register. 0x06 RVAENERGY R 24 0x0 U Same as the VAENERGY register except that the register is reset to 0 following a read operation. 0x07 LVAENERGY R 24 0x0 U Line Accumulation Apparent Energy Register. The instantaneous real power is accumulated in this read-only register over the LINECYC number of half line cycles. 0x08 LVARENERGY R 24 0x0 S Line Accumulation Reactive Energy Register. The instantaneous reactive power is accumulated in this read-only register over the LINECYC number of half line cycles. 0x09 MODE R/W 16 0x000C U Mode Register. This is a 16-bit register through which most of the ADE7753 functionality is accessed. Signal sample rates, filter enabling, and calibration modes are selected by writing to this register. The contents can be read at any time—see the Mode Register (0x9) section. 0x0A IRQEN R/W 16 0x40 U Interrupt Enable Register. ADE7753 interrupts can be deactivated at any time by setting the corresponding bit in this 16- bit enable register to Logic 0. The status register continues to register an interrupt event even if disabled. However, the IRQ output is not activated—see the section. ADE7753 Interrupts 0x0B STATUS R 16 0x0 U Interrupt Status Register. This is an 16-bit read-only register. The status register contains information regarding the source of ADE7753 interrupts—the see ADE7753 Interrupts section. 0x0C RSTSTATUS R 16 0x0 U Same as the interrupt status register except that the register contents are reset to 0 (all flags cleared) after a read operation. 0x0D CH1OS R/W 8 0x00 S* Channel 1 Offset Adjust. Bit 6 is not used. Writing to Bits 0 to 5 allows offsets on Channel 1 to be removed—see the Analog Inputs and CH1OS Register (0x0D) sections. Writing a Logic 1 to the MSB of this register enables the digital integrator on Channel 1, a Logic 0 disables the integrator. The default value of this bit is 0. 0x0E CH2OS R/W 8 0x0 S* Channel 2 Offset Adjust. Bits 6 and 7 are not used. Writing to Bits 0 to 5 of this register allows any offsets on Channel 2 to be removed—see the Analog Inputs section. Note that the CH2OS register is inverted. To apply a positive offset, a negative number is written to this register. 0x0F GAIN R/W 8 0x0 U PGA Gain Adjust. This 8-bit register is used to adjust the gain selection for the PGA in Channels 1 and 2—see the Analog Inputs section. 0x10 PHCAL R/W 6 0x0D S Phase Calibration Register. The phase relationship between Channel 1 and 2 can be adjusted by writing to this 6-bit register. The valid content of this twos compliment register is between 0x1D to 0x21. At a line frequency of 60 Hz, this is a range from –2.06° to +0.7°—see the Phase Compensation section. 0x11 APOS R/W 16 0x0 S Active Power Offset Correction. This 16-bit register allows small offsets in the active power calculation to be removed—see the Active Power Calculation section. ADE7753 Rev. C | Page 53 of 60 Address Name R/W No. Bits Default Type1 Description 0x12 WGAIN R/W 12 0x0 S Power Gain Adjust. This is a 12-bit register. The active power calculation can be calibrated by writing to this register. The calibration range is ±50% of the nominal full-scale active power. The resolution of the gain adjust is 0.0244%/LSB —see the Calibrating an Energy Meter Based on the ADE7753 section. 0x13 WDIV R/W 8 0x0 U Active Energy Divider Register. The internal active energy register is divided by the value of this register before being stored in the AENERGY register. 0x14 CFNUM R/W 12 0x3F U CF Frequency Divider Numerator Register. The output frequency on the CF pin is adjusted by writing to this 12-bit read/write register—see the Energy- to-Frequency Conversion section. 0x15 CFDEN R/W 12 0x3F U CF Frequency Divider Denominator Register. The output frequency on the CF pin is adjusted by writing to this 12-bit read/write register—see the Energy-to-Frequency Conversion section. 0x16 IRMS R 24 0x0 U Channel 1 RMS Value (Current Channel). 0x17 VRMS R 24 0x0 U Channel 2 RMS Value (Voltage Channel). 0x18 IRMSOS R/W 12 0x0 S Channel 1 RMS Offset Correction Register. 0x19 VRMSOS R/W 12 0x0 S Channel 2 RMS Offset Correction Register. 0x1A VAGAIN R/W 12 0x0 S Apparent Gain Register. Apparent power calculation can be calibrated by writing to this register. The calibration range is 50% of the nominal full- scale real power. The resolution of the gain adjust is 0.02444%/LSB. 0x1B VADIV R/W 8 0x0 U Apparent Energy Divider Register. The internal apparent energy register is divided by the value of this register before being stored in the VAENERGY register. 0x1C LINECYC R/W 16 0xFFFF U Line Cycle Energy Accumulation Mode Line-Cycle Register. This 16-bit register is used during line cycle energy accumulation mode to set the number of half line cycles for energy accumulation—see the Line Cycle Energy Accumulation Mode section. 0x1D ZXTOUT R/W 12 0xFFF U Zero-Crossing Timeout. If no zero crossings are detected on Channel 2 within a time period specified by this 12-bit register, the interrupt request line (IRQ) is activated—see the section. Zero-Crossing Detection 0x1E SAGCYC R/W 8 0xFF U Sag Line Cycle Register. This 8-bit register specifies the number of consecutive line cycles the signal on Channel 2 must be below SAGLVL before the SAG output is activated—see the Line Voltage Sag Detection section. 0x1F SAGLVL R/W 8 0x0 U Sag Voltage Level. An 8-bit write to this register determines at what peak signal level on Channel 2 the SAG pin becomes active. The signal must remain low for the number of cycles specified in the SAGCYC register before the SAG pin is activated—see the section. Line Voltage Sag Detection 0x20 IPKLVL R/W 8 0xFF U Channel 1 Peak Level Threshold (Current Channel). This register sets the level of the current peak detection. If the Channel 1 input exceeds this level, the PKI flag in the status register is set. 0x21 VPKLVL R/W 8 0xFF U Channel 2 Peak Level Threshold (Voltage Channel). This register sets the level of the voltage peak detection. If the Channel 2 input exceeds this level, the PKV flag in the status register is set. 0x22 IPEAK R 24 0x0 U Channel 1 Peak Register. The maximum input value of the current channel since the last read of the register is stored in this register. 0x23 RSTIPEAK R 24 0x0 U Same as Channel 1 Peak Register except that the register contents are reset to 0 after read. 0x24 VPEAK R 24 0x0 U Channel 2 Peak Register. The maximum input value of the voltage channel since the last read of the register is stored in this register. 0x25 RSTVPEAK R 24 0x0 U Same as Channel 2 Peak Register except that the register contents are reset to 0 after a read. 0x26 TEMP R 8 0x0 S Temperature Register. This is an 8-bit register which contains the result of the latest temperature conversion—see the Temperature Measurement section. ADE7753 Rev. C | Page 54 of 60 Address Name R/W No. Bits Default Type1 Description 0x27 PERIOD R 16 0x0 U Period of the Channel 2 (Voltage Channel) Input Estimated by Zero- Crossing Processing. The MSB of this register is always zero. 0x28– 0x3C Reserved. 0x3D TMODE R/W 8 – U Test Mode Register. 0x3E CHKSUM R 6 0x0 U Checksum Register. This 6-bit read-only register is equal to the sum of all the ones in the previous read—see the ADE7753 Serial Read Operation section. 0x3F DIEREV R 8 – U Die Revision Register. This 8-bit read-only register contains the revision number of the silicon. 1 Type decoder: U = unsigned, S = signed by twos complement method, and S* = signed by sign magnitude method. ADE7753 Rev. C | Page 55 of 60 ADE7753 REGISTER DESCRIPTIONS All ADE7753 functionality is accessed via the on-chip registers. Each register is accessed by first writing to the communications register and then transferring the register data. A full description of the serial interface protocol is given in the ADE7753 Serial Interface section. COMMUNICATIONS REGISTER The communications register is an 8-bit, write-only register which controls the serial data transfer between the ADE7753 and the host processor. All data transfer operations must begin with a write to the communications register. The data written to the communications register determines whether the next operation is a read or a write and which register is being accessed. Table 13 outlines the bit designations for the communications register. DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 W/R 0 A5 A4 A3 A2 A1 A0 Table 13. Communications Register Bit Location Bit Mnemonic Description 0 to 5 A0 to A5 The six LSBs of the communications register specify the register for the data transfer operation. Table 12 lists the address of each ADE7753 on-chip register. 6 RESERVED This bit is unused and should be set to 0. 7 W/R When this bit is a Logic 1, the data transfer operation immediately following the write to the communications register is interpreted as a write to the ADE7753. When this bit is a Logic 0, the data transfer operation immediately following the write to the communications register is interpreted as a read operation. MODE REGISTER (0x09) The ADE7753 functionality is configured by writing to the mode register. Table 14 describes the functionality of each bit in the register. Table 14. Mode Register Bit Location Bit Mnemonic Default Value Description 0 DISHPF 0 HPF (high-pass filter) in Channel 1 is disabled when this bit is set. 1 DISLPF2 0 LPF (low-pass filter) after the multiplier (LPF2) is disabled when this bit is set. 2 DISCF 1 Frequency output CF is disabled when this bit is set. 3 DISSAG 1 Line voltage sag detection is disabled when this bit is set. 4 ASUSPEND 0 By setting this bit to Logic 1, both ADE7753 A/D converters can be turned off. In normal operation, this bit should be left at Logic 0. All digital functionality can be stopped by suspending the clock signal at CLKIN pin. 5 TEMPSEL 0 Temperature conversion starts when this bit is set to 1. This bit is automatically reset to 0 when the temperature conversion is finished. 6 SWRST 0 Software Chip Reset. A data transfer should not take place to the ADE7753 for at least 18 μs after a software reset. 7 CYCMODE 0 Setting this bit to Logic 1 places the chip into line cycle energy accumulation mode. 8 DISCH1 0 ADC 1 (Channel 1) inputs are internally shorted together. 9 DISCH2 0 ADC 2 (Channel 2) inputs are internally shorted together. 10 SWAP 0 By setting this bit to Logic 1 the analog inputs V2P and V2N are connected to ADC 1 and the analog inputs V1P and V1N are connected to ADC 2. 12, 11 DTRT1, 0 00 These bits are used to select the waveform register update rate. DTRT 1 DTRT0 Update Rate 0 0 27.9 kSPS (CLKIN/128) 0 1 14 kSPS (CLKIN/256) 1 0 7 kSPS (CLKIN/512) 1 1 3.5 kSPS (CLKIN/1024) ADE7753 Rev. C | Page 56 of 60 Bit Location Bit Mnemonic Default Value Description 14, 13 WAVSEL1, 0 00 These bits are used to select the source of the sampled data for the waveform register. WAVSEL1, 0 Length Source 0 0 24 bits active power signal (output of LPF2) 0 1 Reserved 1 0 24 bits Channel 1 1 1 24 bits Channel 2 15 POAM 0 Writing Logic 1 to this bit allows only positive active power to be accumulated in the ADE7753. 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDR: 0x09 SWAP (SWAP CH1 AND CH2 ADCs) DTRT (WAVEFORM SAMPLES OUTPUT DATA RATE) 00 = 27.9kSPS (CLKIN/128) 01 = 14.4kSPS (CLKIN/256) 10 = 7.2kSPS (CLKIN/512) 11 = 3.6kSPS (CLKIN/1024) POAM (POSITIVE ONLY ACCUMULATION) WAVSEL (WAVEFORM SELECTION FOR SAMPLE MODE) 00 = LPF2 01 = RESERVED 10 = CH1 11 = CH2 DISHPF (DISABLE HPF1 IN CHANNEL 1) DISLPF2 (DISABLE LPF2 AFTER MULTIPLIER) DISCF (DISABLE FREQUENCY OUTPUT CF) DISSAG (DISABLE SAG OUTPUT) ASUSPEND (SUSPEND CH1 AND CH2 ADCs) TEMPSEL (START TEMPERATURE SENSING) SWRST (SOFTWARE CHIP RESET) CYCMODE (LINE CYCLE ENERGY ACCUMULATION MODE) DISCH2 (SHORT THE ANALOG INPUTS ON CHANNEL 2) DISCH1 (SHORT THE ANALOG INPUTS ON CHANNEL 1) NOTE: REGISTER CONTENTS SHOW POWER-ON DEFAULTS 02875-0-084 Figure 95. Mode Register ADE7753 Rev. C | Page 57 of 60 INTERRUPT STATUS REGISTER (0x0B), RESET INTERRUPT STATUS REGISTER (0x0C), INTERRUPT ENABLE REGISTER (0x0A) The status register is used by the MCU to determine the source of an interrupt request (IRQ). When an interrupt event occurs in the ADE7753, the corresponding flag in the interrupt status register is set to logic high. If the enable bit for this flag is Logic 1 in the interrupt enable register, the IRQ logic output goes active low. When the MCU services the interrupt, it must first carry out a read from the interrupt status register to determine the source of the interrupt. Table 15. Interrupt Status Register, Reset Interrupt Status Register, and Interrupt Enable Register Bit Location Interrupt Flag Description 0 AEHF Indicates that an interrupt occurred because the active energy register, AENERGY, is more than half full. 1 SAG Indicates that an interrupt was caused by a SAG on the line voltage. 2 CYCEND Indicates the end of energy accumulation over an integer number of half line cycles as defined by the content of the LINECYC register—see the Line Cycle Energy Accumulation Mode section. 3 WSMP Indicates that new data is present in the waveform register. 4 ZX This status bit is set to Logic 0 on the rising and falling edge of the the voltage waveform. See the Zero-Crossing Detection section. 5 TEMP Indicates that a temperature conversion result is available in the temperature register. 6 RESET Indicates the end of a reset (for both software or hardware reset). The corresponding enable bit has no function in the interrupt enable register, i.e., this status bit is set at the end of a reset, but it cannot be enabled to cause an interrupt. 7 AEOF Indicates that the active energy register has overflowed. 8 PKV Indicates that waveform sample from Channel 2 has exceeded the VPKLVL value. 9 PKI Indicates that waveform sample from Channel 1 has exceeded the IPKLVL value. A VAEHF Indicates that an interrupt occurred because the active energy register, VAENERGY, is more than half full. B VAEOF Indicates that the apparent energy register has overflowed. C ZXTO Indicates that an interrupt was caused by a missing zero crossing on the line voltage for the specified number of line cycles—see the Zero-Crossing Timeout section. D PPOS Indicates that the power has gone from negative to positive. E PNEG Indicates that the power has gone from positive to negative. F RESERVED Reserved. 0 0 0 0 0 000 0 000 00 00 89 7 456 23 0115 14 13 12 11 10 AEHF (ACTIVE ENERGY HALF-FULL) ADDR: 0x0A, 0x0B, 0x0C SAG (SAG ONLINE VOLTAGE) CYCEND (END OF LINECYC HALF LINE CYCLES) WSMP (WAVEFORM SAMPLES DATA READY) ZX (ZERO CROSSING) TEMPL (TEMPERATURE DATA READY) RESET (END OF SOFTWARE/HARDWARE RESET) AEOF (ACTIVE ENERGY REGISTER OVERFLOW) VAEHF (VAENERGY IS HALF-FULL) PPOS (POWER NEGATIVE TO POSITIVE) RESERVED PNEG (POWER POSITIVE TO NEGATIVE) ZXTO (ZERO-CROSSING TIMEOUT) VAEOF (VAENERGY OVERFLOW) PK1 (CHANNEL 1 SAMPLE ABOVE IPKLVL) PKV (CHANNEL 2 SAMPLE ABOVE VPKLVL) 02875-A-013 Figure 96. Interrupt Status/Interrupt Enable Register ADE7753 Rev. C | Page 58 of 60 CH1OS REGISTER (0x0D) The CH1OS register is an 8-bit, read/write enabled register. The MSB of this register is used to switch on/off the digital integrator in Channel 1, and Bits 0 to 5 indicates the amount of the offset correction in Channel 1. Table 16 summarizes the function of this register. Table 16. CH1OS Register Bit Location Bit Mnemonic Description 0 to 5 OFFSET The six LSBs of the CH1OS register control the amount of dc offset correction in Channel 1 ADC. The 6-bit offset correction is sign and magnitude coded. Bits 0 to 4 indicate the magnitude of the offset correction. Bit 5 shows the sign of the offset correction. A 0 in Bit 5 means the offset correction is positive and a 1 indicates the offset correction is negative. 6 Not Used This bit is unused. 7 INTEGRATOR This bit is used to activate the digital integrator on Channel 1. The digital integrator is switched on by setting this bit. This bit is set to be 0 on default. DIGITAL INTEGRATOR SELECTION 1 = ENABLE 0 = DISABLE NOT USED 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 ADDR: 0x0D SIGN AND MAGNITUDE CODED OFFSET CORRECTION BITS 02875-0-086 Figure 97. Channel 1 Offset Register ADE7753 Rev. C | Page 59 of 60 OUTLINE DIMENSIONS COMPLIANT TO JEDEC STANDARDS MO-150-AE 06 01 06 -A 20 11 10 1 7.50 7.20 6.90 8.20 7.80 7.40 5.60 5.30 5.00 SEATING PLANE 0.05 MIN 0.65 BSC 2.00 MAX 0.38 0.22COPLANARITY 0.10 1.85 1.75 1.65 0.25 0.09 0.95 0.75 0.55 8° 4° 0° Figure 98. 20-Lead Shrink Small Outline Package [SSOP] (RS-20) Dimensions shown in millimeters ORDERING GUIDE Model1 Temperature Range Package Description Package Option ADE7753ARS −40°C to +85°C 20-Lead Shrink Small Outline Package [SSOP] RS-20 ADE7753ARSRL −40°C to +85°C 20-Lead Shrink Small Outline Package [SSOP] RS-20 ADE7753ARSZ −40°C to +85°C 20-Lead Shrink Small Outline Package [SSOP] RS-20 ADE7753ARSZRL −40°C to +85°C 20-Lead Shrink Small Outline Package [SSOP] RS-20 EVAL-ADE7753ZEB Evaluation Board 1 Z = RoHS Compliant Part. ADE7753 Rev. C | Page 60 of 60 NOTES ©2003–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02875-0-1/10(C)

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